Inventor · disambiguated record
Kevin J. Fischer
Also filed as: FISCHER KEVIN · FISCHER KEVIN J · FISCHER KEVIN JOHN
27 granted patents·14 pending applications·182 citations·filing 2001–2025
96Inventor score
Top patents by PatentIndex Score
41 records- 0195US11239238B2Thin film transistor based memory cells on both sides of a layer of logic devicesINTEL CORP·Filed 2019·Granted Feb 1, 2022·13 cites·23 claims
- 0295US7719062B2Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancementINTEL CORP·Filed 2006·Granted May 18, 2010·33 cites·21 claims
- 0392US8120119B2Stressed barrier plug slot contact structure for transistor performance enhancementFISCHER KEVIN J·Filed 2011·Granted Feb 21, 2012·16 cites·20 claims
- 0491US12170273B2Integrated circuit assemblies with direct chip attach to circuit boardsINTEL CORP·Filed 2021·Granted Dec 17, 2024·2 cites·20 claims
- 0591US9123727B2Airgap interconnect with hood layer and method of formingFISCHER KEVIN·Filed 2011·Granted Sep 1, 2015·27 cites·19 claims
- 0689US7968952B2Stressed barrier plug slot contact structure for transistor performance enhancementINTEL CORP·Filed 2006·Granted Jun 28, 2011·12 cites·10 claims
- 0788US9627312B2On-chip capacitors and methods of assembling sameCHILDS MICHAEL A·Filed 2011·Granted Apr 18, 2017·17 cites·7 claims
- 0885US8278718B2Stressed barrier plug slot contact structure for transistor performance enhancementFISCHER KEVIN J·Filed 2011·Granted Oct 2, 2012·6 cites·16 claims
- 0984US9496173B2Thickened stress relief and power distribution layerINTEL CORP·Filed 2013·Granted Nov 15, 2016·6 cites·25 claims
- 1084US8827550B2Thermal sensor using a vibrating MEMS resonator of a chip interconnect layerABDELMONEUM MOHAMED A·Filed 2009·Granted Sep 9, 2014·17 cites·18 claims
- 1184US8058710B2Interconnects having sealing structures to enable selective metal capping layersHE JUN·Filed 2008·Granted Nov 15, 2011·6 cites·9 claims
- 1284US7402519B2Interconnects having sealing structures to enable selective metal capping layersINTEL CORP·Filed 2005·Granted Jul 22, 2008·6 cites·6 claims
- 1381US12166031B2Substrate-less electrostatic discharge (ESD) integrated circuit structuresINTEL CORP·Filed 2020·Granted Dec 10, 2024·1 cites·20 claims
- 1479US8987859B2Techniques for enhancing dielectric breakdown performanceINTEL CORP·Filed 2012·Granted Mar 24, 2015·8 cites·23 claims
- 1572US9437545B2Interconnects having sealing structures to enable selective metal capping layersINTEL CORP·Filed 2014·Granted Sep 6, 2016·1 cites·6 claims
- 1671US2025254993A1Substrate-free integrated circuit structuresINTEL CORP·Filed 2025·Application pending·0 cites
- 1769US11690211B2Thin film transistor based memory cells on both sides of a layer of logic devicesINTEL CORP·Filed 2021·Granted Jun 27, 2023·0 cites·19 claims
- 1868US2025227968A1Integrated circuit structure with backside power deliveryINTEL CORP·Filed 2025·Application pending·0 cites
- 1967US7525197B2Barrier process/structure for transistor trench contact applicationsINTEL CORP·Filed 2006·Granted Apr 28, 2009·3 cites·9 claims
- 2064US12317590B2Substrate-free integrated circuit structuresINTEL CORP·Filed 2020·Granted May 27, 2025·0 cites·10 claims
- 2161US2023197779A1Integrated circuit structure with backside power deliveryINTEL CORP·Filed 2021·Application pending·0 cites
- 2260US7768126B2Barrier formation and structure to use in semiconductor devicesINTEL CORP·Filed 2006·Granted Aug 3, 2010·2 cites·6 claims
- 2359US9984922B2Interconnects having sealing structures to enable selective metal capping layersINTEL CORP·Filed 2016·Granted May 29, 2018·0 cites·16 claims
- 2459US6607305B2Bi-directional micromechanical latching linear actuatorWISCONSIN ALUMNI RES FOUND·Filed 2001·Granted Aug 19, 2003·6 cites·28 claims
- 2558US2025220870A1Integrated circuit structure with varied epitaxial source or drain structures and device typesINTEL CORP·Filed 2023·Application pending·0 cites
- 2657US10593626B2AVD hardmask for damascene patterningINTEL CORP·Filed 2017·Granted Mar 17, 2020·0 cites·24 claims
- 2756US9780038B2AVD hardmask for damascene patterningINTEL CORP·Filed 2016·Granted Oct 3, 2017·0 cites·12 claims
- 2854US8928125B2Interconnects having sealing structures to enable selective metal capping layersHE JUN·Filed 2011·Granted Jan 6, 2015·0 cites·18 claims
- 2952US2010224960A1Embedded capacitor device and methods of fabricationFISCHER KEVIN JOHN·Filed 2009·Application pending·0 cites
- 3050US2009170309A1Barrier process/structure for transistor trench contact applicationsCHIKARMANE VINAY·Filed 2009·Application pending·0 cites
- 3150US2022415892A1Stacked two-level backend memoryINTEL CORP·Filed 2021·Application pending·0 cites
- 3249US9502281B2AVD hardmask for damascene patterningBRAIN RUTH A·Filed 2011·Granted Nov 22, 2016·0 cites·15 claims
- 3348US10229879B2Thickened stress relief and power distribution layerINTEL CORP·Filed 2016·Granted Mar 12, 2019·0 cites·18 claims
- 3448US2012286395A1Embedded capacitor device and methods of fabricationFISCHER KEVIN JOHN·Filed 2012·Application pending·0 cites
- 3547US2022415780A1Dummy gate patterning lines and integrated circuit structures resulting therefromINTEL CORP·Filed 2021·Application pending·0 cites
- 3646US7582558B2Reducing corrosion in copper damascene processesINTEL CORP·Filed 2006·Granted Sep 1, 2009·0 cites·7 claims
- 3746US2024071831A1Source and drain regions for laterally adjacent gate-all-around (gaa) pmos and nmosINTEL CORP·Filed 2022·Application pending·0 cites
- 3841US2007238309A1Method of reducing interconnect line to line capacitance by using a low k spacerHE JUN·Filed 2006·Application pending·0 cites
- 3939US2008076246A1Through contact layer opening silicide and barrier layer formationPETERSON BRENNAN L·Filed 2006·Application pending·0 cites
- 4035US2003194857A1Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliabilityFiled 2002·Application pending·0 cites
- 4131US2005224980A1Interconnect adapted for reduced electron scatteringLEU JIHPERNG·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →