Inventor · disambiguated record
Ken Jaramillo
Also filed as: JARAMILLO KEN
10 granted patents·1 pending application·221 citations·filing 1997–2001
90Inventor score
Top patents by PatentIndex Score
11 records- 0181US6785854B1Test access port (TAP) controller system and method to debug internal intermediate scan test faultsKONINKL PHILIPS ELECTRONICS NV·Filed 2000·Granted Aug 31, 2004·28 cites·20 claims
- 0270US6016528APriority arbitration system providing low latency and guaranteed access for devicesVLSI TECHNOLOGY INC·Filed 1997·Granted Jan 18, 2000·63 cites·18 claims
- 0369US6598104B1Smart retry system that reduces wasted bus transactions associated with master retriesKONINKL PHILIPS ELECTRONICS NV·Filed 2001·Granted Jul 22, 2003·14 cites·6 claims
- 0464US6301632B1Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocolsVLSI TECHNOLOGY INC·Filed 1999·Granted Oct 9, 2001·48 cites·20 claims
- 0554US5884052ASmart retry mechanism to program the retry latency of a PCI initiator agentVLSI TECHNOLOGY INC·Filed 1997·Granted Mar 16, 1999·29 cites·22 claims
- 0649US6397279B1Smart retry system that reduces wasted bus transactions associated with master retriesVLSI TECHNOLOGY INC·Filed 1998·Granted May 28, 2002·21 cites·9 claims
- 0740US2003093608A1Method for increasing peripheral component interconnect (PCI) bus thoughput via a bridge for memory read transfers via dynamic variable prefetchFiled 2001·Application pending·0 cites
- 0836US6560663B1Method and system for controlling internal busses to prevent bus contention during internal scan testingKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted May 6, 2003·6 cites·14 claims
- 0935US6178477B1Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resourceVLSI TECHNOLOGY INC·Filed 1997·Granted Jan 23, 2001·9 cites·23 claims
- 1029US6523075B1Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resourceKONINKL PHILIPS ELECTRONICS NV·Filed 1999·Granted Feb 18, 2003·1 cites·16 claims
- 1129US6073200ASystem having processor monitoring capability of an integrated circuits buried, internal bus for use with a plurality of internal masters and a method thereforVLSI TECHNOLOGY INC·Filed 1998·Granted Jun 6, 2000·2 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →