Inventor · disambiguated record
Kee Sup Kim
Also filed as: KIM KEE S · KIM KEE SUP
16 granted patents·6 pending applications·415 citations·filing 1993–2025
93Inventor score
Top patents by PatentIndex Score
22 records- 0195US7278074B2System and shadow circuits with output joining circuitINTEL CORP·Filed 2005·Granted Oct 2, 2007·45 cites·26 claims
- 0295US5574733AScan-based built-in self test (BIST) with automatic reseeding of pattern generatorINTEL CORP·Filed 1995·Granted Nov 12, 1996·162 cites·19 claims
- 0390US7185253B2Compacting circuit responsesINTEL CORP·Filed 2002·Granted Feb 27, 2007·40 cites·25 claims
- 0488US7188284B2Error detecting circuitINTEL CORP·Filed 2004·Granted Mar 6, 2007·42 cites·28 claims
- 0587US5504756AMethod and apparatus for multi-frequency, multi-phase scan chainINTEL CORP·Filed 1993·Granted Apr 2, 1996·68 cites·18 claims
- 0686US7523371B2System and shadow bistable circuits coupled to output joining circuitINTEL CORP·Filed 2005·Granted Apr 21, 2009·15 cites·34 claims
- 0782US8522188B2Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chipKIM HYUNG-OCK·Filed 2012·Granted Aug 27, 2013·9 cites·19 claims
- 0872US2025335687A1Cell layout generation device for integrated circuit design, system and method using the sameAXION CO LTD·Filed 2025·Application pending·0 cites
- 0972US2025284872A1Cell layout generation device for ic design, system and method using the sameAXION CO LTD·Filed 2025·Application pending·0 cites
- 1069US6918074B2At speed testing asynchronous signalsINTEL CORP·Filed 2002·Granted Jul 12, 2005·19 cites·35 claims
- 1166US9459680B2System on chip and temperature control method thereofSAMSUNG ELECTRONICS CO LTD·Filed 2013·Granted Oct 4, 2016·3 cites·31 claims
- 1264US9524922B2Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the sameSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Dec 20, 2016·2 cites·20 claims
- 1352US11403452B2Logic yield learning vehicle with phased design windowsSYNOPSYS INC·Filed 2016·Granted Aug 2, 2022·0 cites·21 claims
- 1452US7818642B2Hierarchical test response compaction for a plurality of logic blocksINTEL CORP·Filed 2007·Granted Oct 19, 2010·1 cites·13 claims
- 1552US2025291622A1Virtual Computer Model-Based Fuzz Testing System and MethodKIM KEE SUP·Filed 2025·Application pending·0 cites
- 1652US2025291998A1Ic optimization design device and ic optimization design methodAXION CO LTD·Filed 2025·Application pending·0 cites
- 1751US2025307498A1Design generation device and design generation methodAXION CO LTD·Filed 2025·Application pending·0 cites
- 1841US2013086536A1Method of generating standard cell library for dpl process and methods of producing a dpl mask and circuit pattern using the sameKIM WOOK·Filed 2012·Application pending·0 cites
- 1938US7814383B2Compacting circuit responsesMITRA SUBHASISH·Filed 2005·Granted Oct 12, 2010·0 cites·16 claims
- 2038US7574640B2Compacting circuit responsesINTEL CORP·Filed 2003·Granted Aug 11, 2009·0 cites·15 claims
- 2136US7240260B2Stimulus generationINTEL CORP·Filed 2002·Granted Jul 3, 2007·0 cites·32 claims
- 2235US6076173AArchitectural coverage measureINTEL CORP·Filed 1997·Granted Jun 13, 2000·9 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →