Inventor · disambiguated record
Keshavan Tiruvallur
Also filed as: TIRUVALLUR KESHAVAN · TIRUVALLUR KESHAVAN K
20 granted patents·1 pending application·594 citations·filing 1995–2023
95Inventor score
Top patents by PatentIndex Score
21 records- 0192US7039794B2Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processorINTEL CORP·Filed 2002·Granted May 2, 2006·64 cites·32 claims
- 0291US9043521B2Technique for communicating interrupts in a computer systemINTEL CORP·Filed 2012·Granted May 26, 2015·18 cites·20 claims
- 0390US6496925B1Method and apparatus for processing an event occurrence within a multithreaded processorINTEL CORP·Filed 1999·Granted Dec 17, 2002·117 cites·32 claims
- 0489US7627706B2Creation of logical APIC ID with cluster ID and intra-cluster IDINTEL CORP·Filed 2007·Granted Dec 1, 2009·22 cites·22 claims
- 0589US5724527AFault-tolerant boot strap mechanism for a multiprocessor systemINTEL CORP·Filed 1995·Granted Mar 3, 1998·160 cites·31 claims
- 0688US7769938B2Processor selection for an interrupt identifying a processor clusterINTEL CORP·Filed 2007·Granted Aug 3, 2010·18 cites·22 claims
- 0786US8032681B2Processor selection for an interrupt based on willingness to accept the interrupt and on priorityINTEL CORP·Filed 2007·Granted Oct 4, 2011·15 cites·19 claims
- 0884US8103816B2Technique for communicating interrupts in a computer systemTIRUVALLUR KESHAVAN·Filed 2008·Granted Jan 24, 2012·19 cites·21 claims
- 0978US8312198B2Technique for communicating interrupts in a computer systemTIRUVALLUR KESHAVAN·Filed 2012·Granted Nov 13, 2012·5 cites·24 claims
- 1078US7353370B2Method and apparatus for processing an event occurrence within a multithreaded processorINTEL CORP·Filed 2005·Granted Apr 1, 2008·6 cites·24 claims
- 1172US10198333B2Test, validation, and debug architectureTROBOUGH MARK B·Filed 2010·Granted Feb 5, 2019·6 cites·20 claims
- 1272US7730246B2Opportunistic transmission of software state information within a link based computing systemINTEL CORP·Filed 2005·Granted Jun 1, 2010·5 cites·10 claims
- 1371US6708269B1Method and apparatus for multi-mode fencing in a microprocessor systemINTEL CORP·Filed 1999·Granted Mar 16, 2004·62 cites·25 claims
- 1471US5636374AMethod and apparatus for performing operations based upon the addresses of microinstructionsINTEL CORP·Filed 1995·Granted Jun 3, 1997·68 cites·48 claims
- 1567US8782468B2Methods and tools to debug complex multi-core, multi-socket QPI based systemBHATTACHARYYA BINATA·Filed 2011·Granted Jul 15, 2014·3 cites·20 claims
- 1662US7783809B2Virtualization of pin functionality in a point-to-point interfaceINTEL CORP·Filed 2005·Granted Aug 24, 2010·2 cites·24 claims
- 1759US8423682B2Address space emulationDATTA SHAM M·Filed 2005·Granted Apr 16, 2013·2 cites·20 claims
- 1855US8347018B2Techniques for broadcasting messages on a point-to-point interconnectINTEL CORP·Filed 2009·Granted Jan 1, 2013·0 cites·21 claims
- 1952US7596653B2Technique for broadcasting messages on a point-to-point interconnectINTEL CORP·Filed 2004·Granted Sep 29, 2009·2 cites·19 claims
- 2052US2024320002A1Apparatus and Method for an Efficient System Management ModeINTEL CORP·Filed 2023·Application pending·0 cites
- 2142US8122175B2Opportunistic transmission of software state information within a link based computing systemMURTY KESHAVRAM N·Filed 2010·Granted Feb 21, 2012·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →