Inventor · disambiguated record
Kiran Chikkadi
Also filed as: CHIKKADI KIRAN
4 granted patents·7 pending applications·4 citations·filing 2019–2025
61Inventor score
Top patents by PatentIndex Score
11 records- 0184US11869889B2Self-aligned gate endcap (SAGE) architectures without fin end gapINTEL CORP·Filed 2019·Granted Jan 9, 2024·4 cites·22 claims
- 0274US2025133811A1Self-aligned gate endcap (sage) architectures with improved capINTEL CORP·Filed 2024·Application pending·0 cites
- 0372US12230714B2Self-aligned gate endcap (SAGE) architectures with vertical sidewallsINTEL CORP·Filed 2024·Granted Feb 18, 2025·0 cites·28 claims
- 0472US2024347618A1Self-aligned gate endcap (sage) architectures with improved capINTEL CORP·Filed 2024·Application pending·0 cites
- 0568US2024088143A1Self-aligned gate endcap (sage) architectures without fin end gapINTEL CORP·Filed 2023·Application pending·0 cites
- 0663US2025151318A1Self-aligned gate endcap (sage) architectures with vertical sidewallsINTEL CORP·Filed 2025·Application pending·0 cites
- 0762US2023197826A1Self-aligned gate endcap (sage) architectures with improved capRADLINGER CHRISTINE·Filed 2021·Application pending·0 cites
- 0858US12224349B2Self-aligned gate endcap (SAGE) architectures with vertical sidewallsINTEL CORP·Filed 2020·Granted Feb 11, 2025·0 cites·20 claims
- 0954US2025113516A1Controlled recess of dummy gate to target active transistor portionINTEL CORP·Filed 2023·Application pending·0 cites
- 1052US2025311337A1Dopant engineering to suppress epitaxial misshapenness in n-type epitaxial source-drain transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 1148US11705453B2Self-aligned gate endcap (SAGE) architecture having local interconnectsINTEL CORP·Filed 2019·Granted Jul 18, 2023·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →