Inventor · disambiguated record
Kieu Do
Also filed as: DO KIEU · DO KIEU-HUONG
14 granted patents·109 citations·filing 1992–2020
92Inventor score
Top patents by PatentIndex Score
14 records- 0194US9316689B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2015·Granted Apr 19, 2016·13 cites·20 claims
- 0290US9874608B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2017·Granted Jan 23, 2018·5 cites·20 claims
- 0388US9651619B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2016·Granted May 16, 2017·4 cites·27 claims
- 0487US10365326B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2018·Granted Jul 30, 2019·3 cites·30 claims
- 0582US9689921B2Testing SoC with portable scenario models and at different levelsBreker Verification Systems·Filed 2016·Granted Jun 27, 2017·2 cites·30 claims
- 0681US9310433B2Testing SOC with portable scenario models and at different levelsBreker Verification Systems·Filed 2015·Granted Apr 12, 2016·2 cites·22 claims
- 0774US11748240B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2020·Granted Sep 5, 2023·0 cites·19 claims
- 0873US5353235AWire length minimization in channel compactorVLSI TECHNOLOGY INC·Filed 1992·Granted Oct 4, 1994·63 cites·16 claims
- 0968US11055212B2Testing SoC with portable scenario models and at different levelsBreker Verification Systems·Filed 2019·Granted Jul 6, 2021·0 cites·26 claims
- 1068US10838006B2Scheduling of scenario models for execution within different computer threads and scheduling of memory regions for use with the scenario modelsBreker Verification Systems·Filed 2019·Granted Nov 17, 2020·0 cites·27 claims
- 1162US10429442B2Testing SOC with portable scenario models and at different levelsBreker Verification Systems·Filed 2017·Granted Oct 1, 2019·0 cites·24 claims
- 1260US11113184B2Display in a graphical format of test results generated using scenario modelsBreker Verification Systems·Filed 2016·Granted Sep 7, 2021·0 cites·22 claims
- 1358US9360523B2Display in a graphical format of test results generated using scenario modelsBreker Verification Systems·Filed 2015·Granted Jun 7, 2016·0 cites·3 claims
- 1454US5399517AMethod of routing three layer metal gate arrays using a channel routerVLSI TECHNOLOGY INC·Filed 1992·Granted Mar 21, 1995·17 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →