Inventor · disambiguated record
Kimin Jun
Also filed as: JUN KIMIN
74 granted patents·53 pending applications·196 citations·filing 2011–2025
98Inventor score
Top patents by PatentIndex Score
127 records- 0199US11201221B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2020·Granted Dec 14, 2021·9 cites·24 claims
- 0298US11658221B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2021·Granted May 23, 2023·3 cites·20 claims
- 0398US11594524B2Fabrication and use of through silicon vias on double sided interconnect deviceINTEL CORP·Filed 2022·Granted Feb 28, 2023·6 cites·20 claims
- 0497US12107060B2Microelectronic assemblies with inductors in direct bonding regionsINTEL CORP·Filed 2020·Granted Oct 1, 2024·5 cites·20 claims
- 0597US12062631B2Microelectronic assemblies with inductors in direct bonding regionsINTEL CORP·Filed 2020·Granted Aug 13, 2024·4 cites·20 claims
- 0697US10797139B2Methods of forming backside self-aligned vias and structures formed therebyINTEL CORP·Filed 2019·Granted Oct 6, 2020·22 cites·20 claims
- 0796US10872820B2Integrated circuit structuresINTEL CORP·Filed 2017·Granted Dec 22, 2020·22 cites·11 claims
- 0895US12176323B2Microelectronic assembliesINTEL CORP·Filed 2022·Granted Dec 24, 2024·2 cites·12 claims
- 0995US9685436B2Monolithic three-dimensional (3D) ICs with local inter-level interconnectsINTEL CORP·Filed 2013·Granted Jun 20, 2017·24 cites·24 claims
- 1093US11264493B2Wrap-around source/drain method of making contacts for backside metalsINTEL CORP·Filed 2015·Granted Mar 1, 2022·9 cites·12 claims
- 1192US10367070B2Methods of forming backside self-aligned vias and structures formed therebyINTEL CORP·Filed 2015·Granted Jul 30, 2019·8 cites·21 claims
- 1292US10297592B2Monolithic three-dimensional (3D) ICs with local inter-level interconnectsINTEL CORP·Filed 2017·Granted May 21, 2019·9 cites·16 claims
- 1391US11251156B2Fabrication and use of through silicon vias on double sided interconnect deviceINTEL CORP·Filed 2015·Granted Feb 15, 2022·8 cites·20 claims
- 1491US10068874B2Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)INTEL CORP·Filed 2014·Granted Sep 4, 2018·15 cites·5 claims
- 1590US11251158B2Monolithic chip stacking using a die with double-sided interconnect layersINTEL CORP·Filed 2017·Granted Feb 15, 2022·4 cites·18 claims
- 1689US12199018B2Direct bonding in microelectronic assembliesINTEL CORP·Filed 2020·Granted Jan 14, 2025·2 cites·20 claims
- 1789US2025316650A1Monolithic chip stacking using a die with double-sided interconnect layersINTEL CORP·Filed 2025·Application pending·0 cites
- 1888US12288810B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2024·Granted Apr 29, 2025·0 cites·20 claims
- 1987US10784358B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2015·Granted Sep 22, 2020·3 cites·4 claims
- 2085US12463180B2Monolithic chip stacking using a die with double-sided interconnect layersINTEL CORP·Filed 2023·Granted Nov 4, 2025·0 cites·20 claims
- 2185US11935933B2Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2023·Granted Mar 19, 2024·0 cites·20 claims
- 2285US10043797B2Techniques for forming vertical transistor architecturesINTEL CORP·Filed 2014·Granted Aug 7, 2018·7 cites·25 claims
- 2384US12362325B2Monolithic chip stacking using a die with double-sided interconnect layersINTEL CORP·Filed 2023·Granted Jul 15, 2025·0 cites·14 claims
- 2484US11348897B2Microelectronic assembliesINTEL CORP·Filed 2017·Granted May 31, 2022·3 cites·7 claims
- 2584US2025220952A1Backside contact structures and fabrication for metal on both sides of devicesINTEL CORP·Filed 2025·Application pending·0 cites
- 2683US2024413237A1Wrap-around source/drain method of making contacts for backside metalsINTEL CORP·Filed 2024·Application pending·0 cites
- 2782US11676966B2Stacked transistors having device strata with different channel widthsINTEL CORP·Filed 2019·Granted Jun 13, 2023·2 cites·19 claims
- 2882US10700039B2Silicon die with integrated high voltage devicesINTEL CORP·Filed 2014·Granted Jun 30, 2020·5 cites·13 claims
- 2981US11244943B2Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel materialINTEL CORP·Filed 2019·Granted Feb 8, 2022·2 cites·21 claims
- 3081US2025070083A1Microelectronic assembliesINTEL CORP·Filed 2024·Application pending·0 cites
- 3180US10186484B2Metal on both sides with clock gated-power and signal routing underneathINTEL CORP·Filed 2014·Granted Jan 22, 2019·4 cites·8 claims
- 3279US11393818B2Stacked transistors with Si PMOS and high mobility thin film transistor NMOSINTEL CORP·Filed 2018·Granted Jul 19, 2022·2 cites·24 claims
- 3377US11784165B2Monolithic chip stacking using a die with double-sided interconnect layersINTEL CORP·Filed 2021·Granted Oct 10, 2023·0 cites·20 claims
- 3477US11640961B2III-V source/drain in top NMOS transistors for low temperature stacked transistor contactsINTEL CORP·Filed 2018·Granted May 2, 2023·2 cites·15 claims
- 3577US11393777B2Microelectronic assembliesINTEL CORP·Filed 2017·Granted Jul 19, 2022·2 cites·18 claims
- 3676US2024194533A1Integrated circuit device structures and double-sided electrical testingINTEL CORP·Filed 2023·Application pending·0 cites
- 3775US12100761B2Wrap-around source/drain method of making contacts for backside metalsINTEL CORP·Filed 2022·Granted Sep 24, 2024·0 cites·17 claims
- 3875US12100762B2Wrap-around source/drain method of making contacts for backside metalsINTEL CORP·Filed 2022·Granted Sep 24, 2024·0 cites·20 claims
- 3975US2024355768A1Microelectronic assemblies with inductors in direct bonding regionsINTEL CORP·Filed 2024·Application pending·0 cites
- 4074US10453679B2Methods and devices integrating III-N transistor circuitry with Si transistor circuitryINTEL CORP·Filed 2015·Granted Oct 22, 2019·2 cites·16 claims
- 4173US10439057B2Multi-gate high electron mobility transistors and methods of fabricationINTEL CORP·Filed 2014·Granted Oct 8, 2019·3 cites·15 claims
- 4272US11594452B2Techniques for revealing a backside of an integrated circuit device, and associated configurationsINTEL CORP·Filed 2020·Granted Feb 28, 2023·0 cites·24 claims
- 4371US11721649B2Microelectronic assembliesINTEL CORP·Filed 2022·Granted Aug 8, 2023·0 cites·11 claims
- 4470US11869894B2Metallization structures for stacked device connectivity and their methods of fabricationINTEL CORP·Filed 2022·Granted Jan 9, 2024·0 cites·20 claims
- 4570US11854894B2Integrated circuit device structures and double-sided electrical testingINTEL CORP·Filed 2020·Granted Dec 26, 2023·0 cites·8 claims
- 4669US11996404B2Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel materialINTEL CORP·Filed 2021·Granted May 28, 2024·0 cites·18 claims
- 4769US10490449B2Techniques for revealing a backside of an integrated circuit device, and associated configurationsINTEL CORP·Filed 2015·Granted Nov 26, 2019·1 cites·9 claims
- 4867US10763248B2Multi-layer silicon/gallium nitride semiconductorINTEL CORP·Filed 2015·Granted Sep 1, 2020·1 cites·24 claims
- 4967US2025108459A1Protective debonding stack for selective transferINTEL CORP·Filed 2023·Application pending·0 cites
- 5064US10896847B2Techniques for revealing a backside of an integrated circuit device, and associated configurationsINTEL CORP·Filed 2019·Granted Jan 19, 2021·0 cites·14 claims
Showing the top 50 of 127 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →