Inventor · disambiguated record
Kin Leong Pey
Also filed as: LEONG PEY KIN · PEY KIN L · PEY KIN-LEONG
41 granted patents·2 pending applications·1,401 citations·filing 1992–2018
98Inventor score
Files withCHARTERED SEMICONDUCTOR MFG32GLOBALFOUNDRIES SG PTE LTD4TAN DEXTER XUEMING2LIM YEOW KHENG1LIU WENHU1
Top patents by PatentIndex Score
43 records- 0197US6475908B1Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 5, 2002·128 cites·42 claims
- 0296US5731239AMethod of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistanceCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Mar 24, 1998·174 cites·19 claims
- 0395US6458695B1Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 1, 2002·83 cites·30 claims
- 0492US6365446B1Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing processCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 2, 2002·55 cites·24 claims
- 0592US6153485ASalicide formation on narrow poly lines by pulling back of spacerCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Nov 28, 2000·108 cites·7 claims
- 0692US6025267ASilicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devicesCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Feb 15, 2000·140 cites·27 claims
- 0791US6750519B2Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 15, 2004·45 cites·8 claims
- 0891US6391731B1Activating source and drain junctions and extensions using a single laser annealCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 21, 2002·59 cites·4 claims
- 0987US8338280B2Method for fabricating nano devicesTAN DEXTER·Filed 2010·Granted Dec 25, 2012·17 cites·21 claims
- 1087US6335253B1Method to form MOS transistors with shallow junctions using laser annealingCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jan 1, 2002·49 cites·13 claims
- 1185US6534388B1Method to reduce variation in LDD series resistanceCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 18, 2003·37 cites·10 claims
- 1284US7005716B2Dual metal gate process: metals and their silicidesCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Feb 28, 2006·25 cites·4 claims
- 1383US6677652B2Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jan 13, 2004·24 cites·4 claims
- 1483US6624489B2Formation of silicided shallow junctions using implant through metal technology and laser annealing processCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 23, 2003·25 cites·6 claims
- 1583US6410429B1Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 25, 2002·33 cites·15 claims
- 1682US7253097B2Integrated circuit system using dual damascene processCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 7, 2007·11 cites·20 claims
- 1779US10381360B1Control gate dummy for word line uniformity and method for producing the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2018·Granted Aug 13, 2019·3 cites·18 claims
- 1879US6180501B1Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide processCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jan 30, 2001·44 cites·21 claims
- 1978US7030451B2Method and apparatus for performing nickel salicidationCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Apr 18, 2006·5 cites·10 claims
- 2078US6534390B1Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structureCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 18, 2003·21 cites·26 claims
- 2176US6010954ACmos gate architecture for integration of salicide process in sub 0.1 . .muM devicesCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Jan 4, 2000·41 cites·17 claims
- 2275US6387784B1Method to reduce polysilicon depletion in MOS transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 14, 2002·22 cites·25 claims
- 2375US6093628AUltra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS applicationCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Jul 25, 2000·41 cites·19 claims
- 2474US6271133B1Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabricationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 7, 2001·36 cites·6 claims
- 2573US6339021B1Methods for effective nickel silicide formationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jan 15, 2002·19 cites·22 claims
- 2672US8922003B2Low OHMIC contactsTAN DEXTER XUEMING·Filed 2012·Granted Dec 30, 2014·4 cites·19 claims
- 2772US6566650B1Incorporation of dielectric layer onto SThM tips for direct thermal analysisCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted May 20, 2003·25 cites·18 claims
- 2871US6891233B2Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted May 10, 2005·15 cites·4 claims
- 2971US6284610B1Method to reduce compressive stress in the silicon substrate during silicidationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·19 cites·31 claims
- 3070US6890854B2Method and apparatus for performing nickel salicidationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted May 10, 2005·11 cites·14 claims
- 3169US6524910B1Method of forming dual thickness gate dielectric structures via use of silicon nitride layersCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 25, 2003·13 cites·14 claims
- 3266US6835989B2Methods to form dual metal gates by incorporating metals and their conductive oxidesCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 28, 2004·9 cites·4 claims
- 3366US5956137AIn-line process monitoring using micro-raman spectroscopyCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Sep 21, 1999·31 cites·20 claims
- 3459US9024286B2RRAM cell with bottom electrode(s) positioned in a semiconductor substrateGLOBALFOUNDRIES SG PTE LTD·Filed 2013·Granted May 5, 2015·1 cites·20 claims
- 3559US7892905B2Formation of strained Si channel and Si1-xGex source/drain structures using laser annealingGLOBALFOUNDRIES SG PTE LTD·Filed 2005·Granted Feb 22, 2011·2 cites·40 claims
- 3655US8101487B2Method for fabricating semiconductor devices with shallow diffusion regionsTAN DEXTER XUEMING·Filed 2009·Granted Jan 24, 2012·1 cites·18 claims
- 3754US6316811B1Selective CVD TiSi2 deposition with TiSi2 linerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Nov 13, 2001·5 cites·4 claims
- 3854US5264704AHigh efficiency cathodoluminescence detector with high discrimination against backscattered electronsUNIV SINGAPORE·Filed 1992·Granted Nov 23, 1993·11 cites·15 claims
- 3950US7888224B2Method for forming a shallow junction region using defect engineering and laser annealingUNIV NANYANG TECH·Filed 2008·Granted Feb 15, 2011·0 cites·20 claims
- 4048US2016233157A1Slot designs in wide metal linesGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 4144US9318378B2Slot designs in wide metal linesLIM YEOW KHENG·Filed 2004·Granted Apr 19, 2016·1 cites·18 claims
- 4240US6110811ASelective CVD TiSi2 deposition with TiSi2 linerCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Aug 29, 2000·8 cites·20 claims
- 4340US2012241710A1Fabrication of RRAM Cell Using CMOS Compatible ProcessesLIU WENHU·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →