Inventor · disambiguated record
Kiran Ravi Seth
Also filed as: SETH KIRAN · SETH KIRAN RAVI
6 granted patents·3 pending applications·15 citations·filing 2007–2021
74Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0195US11061677B1Recovering register mapping state of a flushed instruction employing a snapshot of another register mapping state and traversing reorder buffer (ROB) entries in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jul 13, 2021·9 cites·40 claims
- 0285US11113068B1Performing flush recovery using parallel walks of sliced reorder buffers (SROBs)MICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Sep 7, 2021·2 cites·20 claims
- 0381US10877768B1Minimizing traversal of a processor reorder buffer (ROB) for register rename map table (RMT) state recovery for interrupted instruction recovery in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Dec 29, 2020·3 cites·26 claims
- 0451US8127114B2System and method for executing instructions prior to an execution stage in a processorSETH KIRAN RAVI·Filed 2007·Granted Feb 28, 2012·1 cites·16 claims
- 0545US2022398100A1Processors employing memory data bypassing in memory data dependent instructions as a store data forwarding mechanism, and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 0643US10514921B2Fast reuse of physical register namesQUALCOMM INC·Filed 2017·Granted Dec 24, 2019·0 cites·12 claims
- 0741US11803389B2Reach matrix scheduler circuit for scheduling instructions to be executed in a processorMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Oct 31, 2023·0 cites·9 claims
- 0836US2017046160A1Efficient handling of register filesQUALCOMM INC·Filed 2016·Application pending·0 cites
- 0932US2017046164A1High performance recovery from misspeculation of load latencyQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →