Inventor · disambiguated record
Kim Pin Tan
Also filed as: TAN KIM PIN
10 granted patents·1 pending application·60 citations·filing 2002–2022
86Inventor score
Top patents by PatentIndex Score
11 records- 0186US7243315B2Methods for producing structured application-specific integrated circuits that are equivalent to field-programmable gate arraysALTERA CORP·Filed 2005·Granted Jul 10, 2007·18 cites·16 claims
- 0285US6988258B2Mask-programmable logic device with building block architectureALTERA CORP·Filed 2002·Granted Jan 17, 2006·33 cites·39 claims
- 0372US8863061B2Application-specific integrated circuit equivalents of programmable logic and associated methodsALTERA CORP·Filed 2013·Granted Oct 14, 2014·2 cites·20 claims
- 0466US7870513B2Application-specific integrated circuit equivalents of programmable logic and associated methodsALTERA CORP·Filed 2007·Granted Jan 11, 2011·3 cites·12 claims
- 0552US8659334B2Frequency control clock tuning circuitryLIM TEIK WAH·Filed 2012·Granted Feb 25, 2014·1 cites·20 claims
- 0652US8232823B1Frequency control clock tuning circuitryLIM TEIK WAH·Filed 2009·Granted Jul 31, 2012·3 cites·20 claims
- 0746US11941336B2Three-dimensional FPGA with structure ASIC hardening capabilityOPPSTAR TECH SDN BHD·Filed 2021·Granted Mar 26, 2024·0 cites·19 claims
- 0844US8504963B2Application-specific integrated circuit equivalents of programmable logic and associated methodsCHUA KAR KENG·Filed 2012·Granted Aug 6, 2013·0 cites·16 claims
- 0941US8291355B2Application-specific integrated circuit equivalents of programmable logic and associated methodsCHUA KAR KENG·Filed 2010·Granted Oct 16, 2012·0 cites·20 claims
- 1040US12008337B2Multi-input configurable logic cell with configurable output regionOPPSTAR TECH SDN BHD·Filed 2021·Granted Jun 11, 2024·0 cites·20 claims
- 1134US2023288953A1Adjustable clock phase for peak-current reductionOPPSTAR TECH SDN BHD·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →