Inventor · disambiguated record
Klas Olof Lilja
Also filed as: LILJA KLAS · LILJA KLAS OLOF
10 granted patents·6 pending applications·119 citations·filing 1992–2022
89Inventor score
Top patents by PatentIndex Score
16 records- 0192US8566770B2Layout method for soft-error hard electronics, and radiation hardened logic cellLILJA KLAS OLOF·Filed 2011·Granted Oct 22, 2013·12 cites·20 claims
- 0286US8468484B2Layout method for soft-error hard electronics, and radiation hardened logic cellLILJA KLAS OLOF·Filed 2012·Granted Jun 18, 2013·12 cites·6 claims
- 0385US9081926B2Soft error and radiation hardened sequential logic cellLILJA KLAS OLOF·Filed 2013·Granted Jul 14, 2015·6 cites·4 claims
- 0478US8495550B2Soft error hard electronic circuit and layoutLILJA KLAS OLOF·Filed 2010·Granted Jul 23, 2013·6 cites·10 claims
- 0575US5668385APower semiconductor component with transparent emitter and stop layerASEA BROWN BOVERI·Filed 1995·Granted Sep 16, 1997·40 cites·23 claims
- 0668US11374567B2Circuit for low power, radiation hard logic cellLILJA KLAS OLOF·Filed 2017·Granted Jun 28, 2022·2 cites·2 claims
- 0768US9083341B2Soft error resilient circuit design method and logic cellsROBUST CHIP INC·Filed 2012·Granted Jul 14, 2015·4 cites·13 claims
- 0867US5286981ATurn-off power semiconductor component, and also process for producing itASEA BROWN BOVERI·Filed 1992·Granted Feb 15, 1994·29 cites·13 claims
- 0954US11683040B1Circuit architecture and layout for a voting interlocked logic cellLILJA KLAS OLOF·Filed 2022·Granted Jun 20, 2023·0 cites·7 claims
- 1046US2014157223A1Circuit and layout design methods and logic cells for soft error hard integrated circuitsLILJA KLAS OLOF·Filed 2013·Application pending·0 cites
- 1145US2009044158A1Method, and extensions, to couple substrate effects and compact model circuit simulation for efficient simulation of semiconductor devices and circuitLILJA KLAS OLOF·Filed 2008·Application pending·0 cites
- 1244US2016048624A1Circuit and layout design methods and logic cells for soft error hard integrated circuitsLILJA KLAS OLOF·Filed 2015·Application pending·0 cites
- 1344US2009184733A1Layout method for soft-error hard electronics, and radiation hardened logic cellLILJA KLAS OLOF·Filed 2009·Application pending·0 cites
- 1441US2013227499A1Layout method for soft-error hard electronics, and radiation hardened logic cellLILJA KLAS OLOF·Filed 2012·Application pending·0 cites
- 1540US5625203AControlled turn-off power semiconductor deviceASEA BROWN BOVERI·Filed 1995·Granted Apr 29, 1997·8 cites·14 claims
- 1634US2013038348A1Layout method for soft-error hard electronics, and radiation hardened logic cellLILJA KLAS OLOF·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →