Inventor · disambiguated record
Klaus Nierle
Also filed as: NIERLE KLAUS
9 granted patents·5 pending applications·41 citations·filing 2003–2010
85Inventor score
Top patents by PatentIndex Score
14 records- 0181US7263019B2Serial presence detect functionality on memory componentINFINEON TECHNOLOGIES AG·Filed 2005·Granted Aug 28, 2007·10 cites·23 claims
- 0274US7072234B1Method and device for varying an active duty cycle of a wordlineINFINEON TECHNOLOGIES AG·Filed 2005·Granted Jul 4, 2006·10 cites·20 claims
- 0360US7802133B2System and method for addressing errors in a multiple-chip memory deviceQIMONDA NORTH AMERICA CORP·Filed 2007·Granted Sep 21, 2010·4 cites·7 claims
- 0456US7157923B2Method for full wafer contact probing, wafer design and probe card device with reduced probe contactsINFINEON TECHNOLOGIES AG·Filed 2004·Granted Jan 2, 2007·7 cites·22 claims
- 0552US8468401B2Apparatus and method for manufacturing a multiple-chip memory device with multi-stage testingLEE KOONHEE·Filed 2010·Granted Jun 18, 2013·2 cites·7 claims
- 0649US7339841B2Test mode method and apparatus for internal memory timing signalsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Mar 4, 2008·2 cites·25 claims
- 0748US7120070B2Method for testing the serviceability of bit lines in a DRAM memory deviceINFINEON TECHNOLOGIES AG·Filed 2004·Granted Oct 10, 2006·6 cites·12 claims
- 0840US7729186B2Method and system for testing an integrated circuitQIMONDA AG·Filed 2008·Granted Jun 1, 2010·0 cites·19 claims
- 0940US2007038804A1Testmode and test method for increased stress duty cycles during burn inNIERLE KLAUS·Filed 2005·Application pending·0 cites
- 1037US2008285358A1Method and circuit for stressing upper level interconnects in semiconductor devicesQIMONDA NORTH AMERICA CORP·Filed 2007·Application pending·0 cites
- 1131US7385872B2Method and apparatus for increasing clock frequency and data rate for semiconductor devicesQIMONDA NORTH AMERICA CORP·Filed 2006·Granted Jun 10, 2008·0 cites·27 claims
- 1231US2004133827A1Internal data generation and compare via unused external pinsIBM·Filed 2003·Application pending·0 cites
- 1330US2006136791A1Test method, control circuit and system for reduced time combined write window and retention testingNIERLE KLAUS·Filed 2004·Application pending·0 cites
- 1430US2008237587A1Method and circuit for stressing upper level interconnects in semiconductor devicesQIMONDA NORTH AMERICA CORP·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →