Inventor · disambiguated record
Kris G. Konigsfeld
Also filed as: KONIGSFELD KRIS G
24 granted patents·1,410 citations·filing 1994–1997
98Inventor score
Top patents by PatentIndex Score
24 records- 0188US5881262AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1997·Granted Mar 9, 1999·126 cites·45 claims
- 0288US5751983AOut-of-order processor with a memory subsystem which handles speculatively dispatched load operationsFiled 1995·Granted May 12, 1998·140 cites·26 claims
- 0381US5671444AMethods and apparatus for caching data in a non-blocking manner using a plurality of fill buffersINTEL CORPORAITON·Filed 1996·Granted Sep 23, 1997·104 cites·39 claims
- 0481US5420991AApparatus and method for maintaining processing consistency in a computer system having multiple processorsINTEL CORP·Filed 1994·Granted May 30, 1995·89 cites·20 claims
- 0580US5724536AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1994·Granted Mar 3, 1998·74 cites·32 claims
- 0679US5606670AMethod and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer systemINTEL CORP·Filed 1996·Granted Feb 25, 1997·80 cites·32 claims
- 0778US5781790AMethod and apparatus for performing floating point to integer transfers and vice versaINTEL CORP·Filed 1995·Granted Jul 14, 1998·42 cites·21 claims
- 0877US5577200AMethod and apparatus for loading and storing misaligned data on an out-of-order execution computer systemINTEL CORP·Filed 1995·Granted Nov 19, 1996·80 cites·52 claims
- 0971US5636374AMethod and apparatus for performing operations based upon the addresses of microinstructionsINTEL CORP·Filed 1995·Granted Jun 3, 1997·68 cites·48 claims
- 1070US5680572ACache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffersINTEL CORP·Filed 1996·Granted Oct 21, 1997·58 cites·28 claims
- 1166US5778220AMethod and apparatus for disabling interrupts in a highly pipelined processorINTEL CORP·Filed 1996·Granted Jul 7, 1998·47 cites·16 claims
- 1266US5748937AComputer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructionsINTEL CORP·Filed 1997·Granted May 5, 1998·47 cites·17 claims
- 1365US5826109AMethod and apparatus for performing multiple load operations to the same memory location in a computer systemINTEL CORP·Filed 1996·Granted Oct 20, 1998·49 cites·18 claims
- 1465US5694574AMethod and apparatus for performing load operations in a computer systemINTEL CORP·Filed 1996·Granted Dec 2, 1997·48 cites·53 claims
- 1565US5664137AMethod and apparatus for executing and dispatching store operations in a computer systemINTEL CORP·Filed 1995·Granted Sep 2, 1997·52 cites·49 claims
- 1664US5898854AApparatus for indicating an oldest non-retired load operation in an arrayINTEL CORP·Filed 1995·Granted Apr 27, 1999·45 cites·22 claims
- 1762US5721857AMethod and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessorINTEL CORP·Filed 1996·Granted Feb 24, 1998·41 cites·19 claims
- 1862US5588126AMethods and apparatus for fordwarding buffered store data on an out-of-order execution computer systemINTEL CORP·Filed 1995·Granted Dec 24, 1996·36 cites·8 claims
- 1961US5860154AMethod and apparatus for calculating effective memory addressesINTEL CORP·Filed 1997·Granted Jan 12, 1999·39 cites·14 claims
- 2060US5717882AMethod and apparatus for dispatching and executing a load operation to memoryINTEL CORP·Filed 1996·Granted Feb 10, 1998·37 cites·34 claims
- 2159US5434987AMethod and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered storeINTEL CORP·Filed 1994·Granted Jul 18, 1995·33 cites·24 claims
- 2257US6378062B1Method and apparatus for performing a store operationINTEL CORP·Filed 1997·Granted Apr 23, 2002·32 cites·63 claims
- 2350US5694553AMethod and apparatus for determining the dispatch readiness of buffered load operations in a processorINTEL CORP·Filed 1995·Granted Dec 2, 1997·23 cites·8 claims
- 2448US5708843AMethod and apparatus for handling code segment violations in a computer systemINTEL CORP·Filed 1995·Granted Jan 13, 1998·20 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →