Inventor · disambiguated record
Kurt F. Baty
Also filed as: BATY KURT · BATY KURT F
14 granted patents·654 citations·filing 1981–2018
94Inventor score
Files withSTRATUS COMPUTER INC9EVERSPIN TECHNOLOGIES INC3EVERSPIN TECHONOLGIES INC1STRATUS COMPUTER1
Top patents by PatentIndex Score
14 records- 0193US10102064B1Two layer quad bit error correctionEVERSPIN TECHNOLOGIES INC·Filed 2015·Granted Oct 16, 2018·11 cites·12 claims
- 0293US4654857ADigital data processor with high reliabilitySTRATUS COMPUTER INC·Filed 1985·Granted Mar 31, 1987·206 cites·36 claims
- 0393US4486826AComputer peripheral control apparatusSTRATUS COMPUTER INC·Filed 1981·Granted Dec 4, 1984·132 cites·9 claims
- 0484US4750177ADigital data processor apparatus with pipelined fault tolerant bus protocolSTRATUS COMPUTER INC·Filed 1986·Granted Jun 7, 1988·98 cites·35 claims
- 0574US4931922AMethod and apparatus for monitoring peripheral device communicationsSTRATUS COMPUTER INC·Filed 1987·Granted Jun 5, 1990·36 cites·20 claims
- 0672US4974150AFault tolerant digital data processor with improved input/output controllerSTRATUS COMPUTER INC·Filed 1989·Granted Nov 27, 1990·33 cites·16 claims
- 0768US4974144ADigital data processor with fault-tolerant peripheral interfaceSTRATUS COMPUTER INC·Filed 1989·Granted Nov 27, 1990·27 cites·19 claims
- 0867US10503593B2Two layer quad bit error correctionEVERSPIN TECHONOLGIES INC·Filed 2018·Granted Dec 10, 2019·2 cites·20 claims
- 0964US4926315ADigital data processor with fault tolerant peripheral bus communicationsSTRATUS COMPUTER INC·Filed 1987·Granted May 15, 1990·24 cites·15 claims
- 1061US4920540AFault-tolerant digital timing apparatus and methodSTRATUS COMPUTER INC·Filed 1987·Granted Apr 24, 1990·29 cites·2 claims
- 1160US4939643AFault tolerant digital data processor with improved bus protocolSTRATUS COMPUTER INC·Filed 1987·Granted Jul 3, 1990·20 cites·48 claims
- 1259US10657014B2Methods for monitoring and managing memory devicesEVERSPIN TECHNOLOGIES INC·Filed 2018·Granted May 19, 2020·1 cites·19 claims
- 1357US5243704AOptimized interconnect networksSTRATUS COMPUTER·Filed 1992·Granted Sep 7, 1993·35 cites·40 claims
- 1442US10348333B2Two bit error correction via a field programmable gate arrayEVERSPIN TECHNOLOGIES INC·Filed 2017·Granted Jul 9, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →