Inventor · disambiguated record
Kurt A. Feiste
Also filed as: FEISTE KURT A · FEISTE KURT ALAN
42 granted patents·8 pending applications·633 citations·filing 1995–2021
98Inventor score
Technology areasG06F
Files withIBM46ABERNATHY CHRISTOPHER M1ABERNATHY CHRISTOPHER MICHAEL1DEMENT JONATHAN J1DEMENT JONATHAN JAMES1
Top patents by PatentIndex Score
50 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0295US8041928B2Information handling system with real and virtual load/store instruction issue queueIBM·Filed 2008·Granted Oct 18, 2011·46 cites·20 claims
- 0392US7350056B2Method and apparatus for issuing instructions from an issue queue in an information handling systemIBM·Filed 2005·Granted Mar 25, 2008·32 cites·17 claims
- 0486US7437539B2Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 14, 2008·13 cites·10 claims
- 0585US7412589B2Method to detect a stalled instruction stream and serialize micro-operation executionIBM·Filed 2006·Granted Aug 12, 2008·13 cites·10 claims
- 0684US6021485AForwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matchingIBM·Filed 1997·Granted Feb 1, 2000·113 cites·24 claims
- 0782US10936321B2Instruction chainingIBM·Filed 2019·Granted Mar 2, 2021·3 cites·20 claims
- 0878US7434033B2Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 7, 2008·7 cites·11 claims
- 0975US7818544B2Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock conditionIBM·Filed 2008·Granted Oct 19, 2010·5 cites·20 claims
- 1074US8082423B2Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updatesABERNATHY CHRISTOPHER MICHAEL·Filed 2005·Granted Dec 20, 2011·7 cites·1 claims
- 1170US8200946B2Issue unit for placing a processor into a gradual slow mode of operationABERNATHY CHRISTOPHER M·Filed 2008·Granted Jun 12, 2012·4 cites·20 claims
- 1270US6349382B1System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program orderIBM·Filed 1999·Granted Feb 19, 2002·56 cites·9 claims
- 1367US10496412B2Parallel dispatching of multi-operation instructions in a multi-slice computer processorIBM·Filed 2016·Granted Dec 3, 2019·1 cites·14 claims
- 1467US5926830AData processing system and method for maintaining coherency between high and low level caches using inclusive statesIBM·Filed 1996·Granted Jul 20, 1999·50 cites·8 claims
- 1563US7370176B2System and method for high frequency stall designIBM·Filed 2005·Granted May 6, 2008·2 cites·6 claims
- 1662US7949857B2Method and system for determining multiple unused registers in a processorIBM·Filed 2008·Granted May 24, 2011·2 cites·15 claims
- 1762US6134646ASystem and method for executing and completing store instructionsIBM·Filed 1999·Granted Oct 17, 2000·42 cites·16 claims
- 1862US5963978AHigh level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicatorsIBM·Filed 1996·Granted Oct 5, 1999·39 cites·10 claims
- 1962US2019294571A1Operation of a multi-slice processor implementing datapath steeringIBM·Filed 2019·Application pending·0 cites
- 2061US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 2159US10970079B2Parallel dispatching of multi-operation instructions in a multi-slice computer processorIBM·Filed 2019·Granted Apr 6, 2021·0 cites·14 claims
- 2259US10838728B2Parallel slice processor shadowing states of hardware threads across execution slicesIBM·Filed 2018·Granted Nov 17, 2020·0 cites·18 claims
- 2358US11327766B2Instruction dispatch routingIBM·Filed 2020·Granted May 10, 2022·0 cites·24 claims
- 2458US10671399B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·8 claims
- 2558US10437756B2Operation of a multi-slice processor implementing datapath steeringIBM·Filed 2016·Granted Oct 8, 2019·0 cites·7 claims
- 2657US10671398B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·12 claims
- 2757US10417152B2Operation of a multi-slice processor implementing datapath steeringIBM·Filed 2016·Granted Sep 17, 2019·0 cites·13 claims
- 2857US10102001B2Parallel slice processor shadowing states of hardware threads across execution slicesIBM·Filed 2018·Granted Oct 16, 2018·0 cites·18 claims
- 2957US7953960B2Method and apparatus for delaying a load miss flush until issuing the dependent instructionIBM·Filed 2005·Granted May 31, 2011·1 cites·21 claims
- 3056US5832276AResolving processor and system bus address collision in a high-level cacheIBM·Filed 1996·Granted Nov 3, 1998·36 cites·14 claims
- 3155US6658534B1Mechanism to reduce instruction cache miss penalties and methods thereforIBM·Filed 1998·Granted Dec 2, 2003·28 cites·33 claims
- 3254US6266767B1Apparatus and method for facilitating out-of-order execution of load instructionsIBM·Filed 1999·Granted Jul 24, 2001·28 cites·20 claims
- 3353US10877763B2Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processorIBM·Filed 2018·Granted Dec 29, 2020·0 cites·18 claims
- 3453US9977677B2Execution slice with supplemental instruction port for an instruction using a source operand from another instruction portIBM·Filed 2016·Granted May 22, 2018·0 cites·18 claims
- 3553US2008294885A1Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation ExecutionIBM·Filed 2008·Application pending·0 cites
- 3652US12204902B2Routing instruction results to a register block of a subdivided register file based on register block utilization rateIBM·Filed 2021·Granted Jan 21, 2025·0 cites·15 claims
- 3752US6070238AMethod and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instructionIBM·Filed 1997·Granted May 30, 2000·25 cites·14 claims
- 3852US2008148021A1High Frequency Stall DesignDEMENT JONATHAN JAMES·Filed 2008·Application pending·0 cites
- 3951US5822765ASystem and method for resolving contention arising from execution of cache coherency operations in a multiple cache computer systemIBM·Filed 1995·Granted Oct 13, 1998·27 cites·11 claims
- 4049US10120683B2Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)IBM·Filed 2016·Granted Nov 6, 2018·0 cites·20 claims
- 4147US5860100APipelined flushing of a high level cache and invalidation of lower level cachesIBM·Filed 1996·Granted Jan 12, 1999·25 cites·10 claims
- 4243US10740107B2Operation of a multi-slice processor implementing load-hit-store handlingIBM·Filed 2016·Granted Aug 11, 2020·0 cites·17 claims
- 4343US9971687B2Operation of a multi-slice processor with history buffers storing transaction memory state informationIBM·Filed 2016·Granted May 15, 2018·0 cites·12 claims
- 4443US2007198812A1Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling systemIBM·Filed 2005·Application pending·0 cites
- 4543US2004111594A1Multithreading recycle and dispatch mechanismIBM·Filed 2002·Application pending·0 cites
- 4643US2006224864A1System and method for handling multi-cycle non-pipelined instruction sequencingDEMENT JONATHAN J·Filed 2005·Application pending·0 cites
- 4740US2018004516A1Administering instruction tags in a computer processorIBM·Filed 2016·Application pending·0 cites
- 4840US2018107510A1Operation of a multi-slice processor implementing instruction fusionIBM·Filed 2016·Application pending·0 cites
- 4934US5974259AData processing system and method of operation having input/output drivers with reduced power consumption and noise levelsIBM·Filed 1996·Granted Oct 26, 1999·8 cites·20 claims
- 5030US6167500AMechanism for queuing store data and method thereforIBM·Filed 1998·Granted Dec 26, 2000·1 cites·35 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →