Inventor · disambiguated record
Kuo-Reay Peng
Also filed as: PENG KUO-REAY
25 granted patents·2 pending applications·1,128 citations·filing 1997–2004
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG27
Top patents by PatentIndex Score
27 records- 0197US6329234B1Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flowTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Dec 11, 2001·212 cites·34 claims
- 0293US6614693B1Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROMTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Sep 2, 2003·77 cites·72 claims
- 0392US6472721B2Dual damascene interconnect structures that include radio frequency capacitors and inductorsTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Oct 29, 2002·60 cites·13 claims
- 0490US6645820B1Polycrystalline silicon diode string for ESD protection of different power supply connectionsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 11, 2003·50 cites·9 claims
- 0590US6610262B1Depletion mode SCR for low capacitance ESD input protectionTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Aug 26, 2003·46 cites·21 claims
- 0690US6122201AClipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROMTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 19, 2000·79 cites·39 claims
- 0790US5828605ASnapback reduces the electron and hole trapping in the tunneling oxide of flash EEPROMTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Oct 27, 1998·95 cites·12 claims
- 0884US6049486ATriple mode erase scheme for improving flash EEPROM cell threshold voltage (VT) cycling closure effectTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 11, 2000·57 cites·59 claims
- 0983US6055183AErase method of flash EEPROM by using snapback characteristicTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Apr 25, 2000·54 cites·16 claims
- 1082US5862078AMixed mode erase method to improve flash eeprom write/erase threshold closureTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jan 19, 1999·56 cites·22 claims
- 1180US6448123B1Low capacitance ESD protection deviceTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Sep 10, 2002·27 cites·5 claims
- 1279US6049484AErase method to improve flash EEPROM endurance by combining high voltage source erase and negative gate eraseTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Apr 11, 2000·43 cites·20 claims
- 1379US5726933AClipped sine shaped waveform to reduce the cycling-induced electron trapping in the tunneling oxide of flash EEPROMTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Mar 10, 1998·43 cites·10 claims
- 1476US5949717AMethod to improve flash EEPROM cell write/erase threshold voltage closureTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Sep 7, 1999·41 cites·24 claims
- 1575US6661060B2Low capacitance ESD protection deviceTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Dec 9, 2003·20 cites·23 claims
- 1671US6881996B2Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layerTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Apr 19, 2005·15 cites·8 claims
- 1770US6876041B2ESD protection componentTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Apr 5, 2005·15 cites·4 claims
- 1869US5913122AMethod of making high breakdown voltage twin well device with source/drain regions widely spaced from FOX regionsTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jun 15, 1999·27 cites·20 claims
- 1966US6303454B1Process for a snap-back flash EEPROM cellTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·14 cites·14 claims
- 2065US6812088B1Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 2, 2004·11 cites·19 claims
- 2163US5838618ABi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closureTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Nov 17, 1998·23 cites·32 claims
- 2262US6667217B1Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS processTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 23, 2003·12 cites·9 claims
- 2362US5903499AMethod to erase a flash EEPROM using negative gate source erase followed by a high negative gate eraseTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted May 11, 1999·21 cites·24 claims
- 2459US5950087AMethod to make self-aligned source etching available in split-gate flashTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Sep 7, 1999·20 cites·38 claims
- 2548US6025628AHigh breakdown voltage twin well device with source/drain regions widely spaced from fox regionsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Feb 15, 2000·10 cites·14 claims
- 2639US2004070902A1Polycrystalline silicon diode string for ESD protection of different power supply connectionsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 2738US2004004231A1Depletion mode SCR for low capacitance ESD input protectionTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →