Inventor · disambiguated record
Kunal Vaed
Also filed as: VAED KUNAL
23 granted patents·5 pending applications·228 citations·filing 2002–2012
96Inventor score
Top patents by PatentIndex Score
28 records- 0194US7662722B2Air gap under on-chip passive deviceIBM·Filed 2007·Granted Feb 16, 2010·31 cites·17 claims
- 0290US7361950B2Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectricIBM·Filed 2005·Granted Apr 22, 2008·17 cites·17 claims
- 0388US7545007B2MOS varactor with segmented gate dopingIBM·Filed 2005·Granted Jun 9, 2009·18 cites·9 claims
- 0487US7394145B2Methods of fabricating passive element without planarizing and related semiconductor deviceIBM·Filed 2007·Granted Jul 1, 2008·10 cites·9 claims
- 0586US7439151B2Method and structure for integrating MIM capacitors within dual damascene processing techniquesIBM·Filed 2006·Granted Oct 21, 2008·12 cites·19 claims
- 0686US7410894B2Post last wiring level inductor using patterned plate processIBM·Filed 2005·Granted Aug 12, 2008·9 cites·8 claims
- 0785US7608909B2Suspended transmission line structures in back end of line processingIBM·Filed 2005·Granted Oct 27, 2009·12 cites·9 claims
- 0884US7622357B2Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistanceIBM·Filed 2006·Granted Nov 24, 2009·13 cites·6 claims
- 0983US7763954B2Post last wiring level inductor using patterned plate processIBM·Filed 2008·Granted Jul 27, 2010·7 cites·10 claims
- 1083US7573117B2Post last wiring level inductor using patterned plate processIBM·Filed 2008·Granted Aug 11, 2009·7 cites·8 claims
- 1181US7741698B2Post last wiring level inductor using patterned plate processIBM·Filed 2008·Granted Jun 22, 2010·6 cites·10 claims
- 1281US6992344B2Damascene integration scheme for developing metal-insulator-metal capacitorsIBM·Filed 2002·Granted Jan 31, 2006·24 cites·14 claims
- 1379US7910450B2Method of fabricating a precision buried resistorIBM·Filed 2006·Granted Mar 22, 2011·7 cites·10 claims
- 1478US7915134B2Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric materialIBM·Filed 2008·Granted Mar 29, 2011·6 cites·19 claims
- 1578US7427550B2Methods of fabricating passive element without planarizingIBM·Filed 2006·Granted Sep 23, 2008·5 cites·9 claims
- 1678US7005371B2Method of forming suspended transmission line structures in back end of line processingIBM·Filed 2004·Granted Feb 28, 2006·22 cites·10 claims
- 1777US7691717B2Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereofIBM·Filed 2006·Granted Apr 6, 2010·5 cites·9 claims
- 1871US6940117B2Prevention of Ta2O5 mim cap shorting in the beol anneal cyclesIBM·Filed 2003·Granted Sep 6, 2005·13 cites·18 claims
- 1968US7732294B2Post last wiring level inductor using patterned plate processIBM·Filed 2008·Granted Jun 8, 2010·2 cites·3 claims
- 2066US8119491B2Methods of fabricating passive element without planarizing and related semiconductor deviceCHINTHAKINDI ANIL K·Filed 2008·Granted Feb 21, 2012·2 cites·10 claims
- 2154US7732295B2Post last wiring level inductor using patterned plate processIBM·Filed 2008·Granted Jun 8, 2010·0 cites·6 claims
- 2253US8487401B2Methods of fabricating passive element without planarizing and related semiconductor deviceCHINTHAKINDI ANIL K·Filed 2012·Granted Jul 16, 2013·0 cites·6 claims
- 2351US2008185684A1Method and structure for integrating mim capacitors within dual damascene processing techniquesIBM·Filed 2008·Application pending·0 cites
- 2444US7354872B2Hi-K dielectric layer deposition methodsIBM·Filed 2005·Granted Apr 8, 2008·0 cites·20 claims
- 2544US2011108919A1Method of fabricating a precision buried resistorIBM·Filed 2011·Application pending·0 cites
- 2643US2008173981A1Integrated circuit (ic) chip with one or more vertical plate capacitors and method of making the capacitorsCHINTHAKINDI ANIL K·Filed 2007·Application pending·0 cites
- 2742US2007152332A1Single or dual damascene via level wirings and/or devices, and methods of fabricating sameIBM·Filed 2006·Application pending·0 cites
- 2836US2005062137A1Vertically-stacked co-planar transmission line structure for IC designIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →