Inventor · disambiguated record
Kuo-Chien Wu
Also filed as: WU KUO C · WU KUO-CHIEN
20 granted patents·8 pending applications·98 citations·filing 1997–2005
93Inventor score
Top patents by PatentIndex Score
28 records- 0176US6797611B1Method of fabricating contact holes on a semiconductor chipNANYA TECHNOLOGY CORP·Filed 2003·Granted Sep 28, 2004·24 cites·20 claims
- 0268US7115491B2Method for forming self-aligned contact in semiconductor deviceNANYA TECHNOLOGY CORP·Filed 2004·Granted Oct 3, 2006·15 cites·16 claims
- 0368US6960503B2Method for fabricating a trench capacitorNANYA TECHNOLOGY CORP·Filed 2003·Granted Nov 1, 2005·14 cites·11 claims
- 0465US6979613B1Method for fabricating a trench capacitor of DRAMNANYA TECHNOLOGY CORP·Filed 2003·Granted Dec 27, 2005·12 cites·10 claims
- 0561US6960530B2Method of reducing the aspect ratio of a trenchNANYA TECHNOLOGY CORP·Filed 2003·Granted Nov 1, 2005·8 cites·20 claims
- 0651US6790771B2Bitline structure for DRAM and method of forming the sameNANYA TECHNOLOGY CORP·Filed 2003·Granted Sep 14, 2004·4 cites·13 claims
- 0750US6743717B1Method for forming silicide at source and drainNANYA TECHNOLOGY CORP·Filed 2003·Granted Jun 1, 2004·4 cites·20 claims
- 0849US6953725B2Method for fabricating memory device having a deep trench capacitorNANYA TECHNOLOGY CORP·Filed 2003·Granted Oct 11, 2005·4 cites·19 claims
- 0948US6991978B2World line structure with single-sided partially recessed gate structureNANYA TECHNOLOGY CORP·Filed 2004·Granted Jan 31, 2006·3 cites·11 claims
- 1048US6797564B1Method of forming bit lines and bit line contacts in a memory deviceNANYA TECHNOLOGY CORP·Filed 2003·Granted Sep 28, 2004·3 cites·16 claims
- 1146US7358576B2Word line structure with single-sided partially recessed gate structureNANYA TECHNOLOGY CORP·Filed 2005·Granted Apr 15, 2008·0 cites·6 claims
- 1246US6933229B2Method of manufacturing semiconductor device featuring formation of conductive plugsNANYA TECHNOLOGY CORP·Filed 2003·Granted Aug 23, 2005·2 cites·12 claims
- 1344US2005275109A1Semiconductor device and fabricating method thereofKUAN SHIH-FAN·Filed 2005·Application pending·0 cites
- 1442US6972248B2Method of fabricating semiconductor deviceNANYA TECHNOLOGY CORP·Filed 2004·Granted Dec 6, 2005·1 cites·19 claims
- 1541US7075138B2Bitline structure for DRAM and method of forming the sameNANYA TECHNOLOGY CORP·Filed 2004·Granted Jul 11, 2006·0 cites·6 claims
- 1638US7030011B2Method for avoiding short-circuit of conductive wiresNANYA TECHNOLOGY CORP·Filed 2003·Granted Apr 18, 2006·0 cites·18 claims
- 1738US2005020059A1Method for forming aluminum-containing interconnectFiled 2004·Application pending·0 cites
- 1837US7052949B2Method for forming bit lineNANYA TECHNOLOGY CORP·Filed 2003·Granted May 30, 2006·0 cites·8 claims
- 1937US2004058519A1Method for forming bit line contactNANYA TECHNOLOGY CORP·Filed 2002·Application pending·0 cites
- 2037US2005032389A1Method for avoiding erosion of DRAM fuse sidewallNANYA TECHNOLOGY CORP·Filed 2003·Application pending·0 cites
- 2137US2005260847A1Method for forming contact windowYANG J H·Filed 2004·Application pending·0 cites
- 2236US2005003307A1Method for forming DRAM cell bit-line contactFiled 2003·Application pending·0 cites
- 2335US7033885B2Deep trench structure manufacturing processNANYA TECHNOLOGY CORP·Filed 2003·Granted Apr 25, 2006·0 cites·6 claims
- 2435US6943099B2Method for manufacturing gate structure with sides of its metal layer partially removedNANYA TECHNOLOGY CORP·Filed 2004·Granted Sep 13, 2005·0 cites·10 claims
- 2535US2005124127A1Method for manufacturing gate structure for use in semiconductor deviceFiled 2003·Application pending·0 cites
- 2634US6930043B2Method for forming DRAM cell bit line and bit line contact structureNANYA TECHNOLOGY CORP·Filed 2003·Granted Aug 16, 2005·0 cites·2 claims
- 2734US5888904AMethod for manufacturing polysilicon with relatively small line widthHOLTEK MICROELECTRONICS INC·Filed 1997·Granted Mar 30, 1999·4 cites·14 claims
- 2834US2005176244A1Method for manufacturing gate structure of memoryNANYA TECHNOLOGY CORP·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →