Inventor · disambiguated record
Kwang-Ting Cheng
Also filed as: CHENG KWANG T · CHENG KWANG-TING
17 granted patents·2 pending applications·697 citations·filing 1989–2025
95Inventor score
Files withLUCENT TECHNOLOGIES INC4AT & T BELL LAB3AGERE SYSTEMS INC2UNIV HONG KONG SCIENCE & TECH2VIMA TECHNOLOGIES INC2
Top patents by PatentIndex Score
19 records- 0195US6345373B1System and method for testing high speed VLSI devices using slower testersUNIV CALIFORNIA·Filed 1999·Granted Feb 5, 2002·157 cites·7 claims
- 0293US5043986AMethod and integrated circuit adapted for partial scan testabilityAT & T BELL LAB·Filed 1989·Granted Aug 27, 1991·86 cites·11 claims
- 0385US6694466B1Method and system for improving the test quality for scan-based BIST using a general test application schemeAGERE SYSTEMS INC·Filed 1999·Granted Feb 17, 2004·62 cites·19 claims
- 0483US6976016B2Maximizing expected generalization for learning complex query conceptsVIMA TECHNOLOGIES INC·Filed 2001·Granted Dec 13, 2005·50 cites·24 claims
- 0579US7158970B2Maximizing expected generalization for learning complex query conceptsVIMA TECHNOLOGIES INC·Filed 2002·Granted Jan 2, 2007·27 cites·26 claims
- 0679US6463561B1Almost full-scan BIST method and system having higher fault coverage and shorter test application timeAGERE SYST GUARDIAN CORP·Filed 1999·Granted Oct 8, 2002·46 cites·2 claims
- 0778US5257268ACost-function directed search method for generating tests for sequential logic circuitsAT & T BELL LAB·Filed 1990·Granted Oct 26, 1993·41 cites·2 claims
- 0873US6256759B1Hybrid algorithm for test point selection for scan-based BISTAGERE SYSTEMS INC·Filed 1998·Granted Jul 3, 2001·75 cites·19 claims
- 0968US5513122AMethod and apparatus for determining the reachable states in a hybrid model state machineAT & T CORP·Filed 1994·Granted Apr 30, 1996·47 cites·20 claims
- 1066US11444124B2Hybrid memristor/field-effect transistor memory cell and its information encoding schemeUNIV HONG KONG SCIENCE & TECH·Filed 2018·Granted Sep 13, 2022·3 cites·20 claims
- 1160US5587919AApparatus and method for logic optimization by redundancy addition and removalLUCENT TECHNOLOGIES INC·Filed 1994·Granted Dec 24, 1996·25 cites·38 claims
- 1260US5228040ATestable implementations of finite state machines and methods for producing themAT & T BELL LAB·Filed 1990·Granted Jul 13, 1993·21 cites·21 claims
- 1359US5590135ATesting a sequential circuitLUCENT TECHNOLOGIES INC·Filed 1991·Granted Dec 31, 1996·21 cites·1 claims
- 1454US12483626B2Sensor systemUNIV HONG KONG SCIENCE & TECH·Filed 2024·Granted Nov 25, 2025·0 cites·19 claims
- 1554US2025315571A1System and method for neural network accelerator and toolchain design automationAI CHIP CENTER FOR EMERGING SMART SYSTEMS LTD·Filed 2025·Application pending·0 cites
- 1651US6018813AIdentification and test generation for primitive faultsNEC USA INC·Filed 1997·Granted Jan 25, 2000·16 cites·8 claims
- 1746US5828828AMethod for inserting test points for full-and-partial-scan built-in self-testingLUCENT TECHNOLOGIES INC·Filed 1997·Granted Oct 27, 1998·12 cites·3 claims
- 1842US2003016250A1Computer user interface for perception-based information retrievalFiled 2002·Application pending·0 cites
- 1938US5710711AMethod and integrated circuit adapted for partial scan testabilityLUCENT TECHNOLOGIES INC·Filed 1995·Granted Jan 20, 1998·8 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →