Inventor · disambiguated record
Kyoung-Woo Lee
Also filed as: LEE KYOUNG W · LEE KYOUNG WOO
59 granted patents·19 pending applications·968 citations·filing 1998–2025
99Inventor score
Files withSAMSUNG ELECTRONICS CO LTD62LEE KYOUNG WOO6LG ELECTRONICS INC2CHOO JAE-OUK1INFINEON TECHNOLOGIES AG1
Top patents by PatentIndex Score
78 records- 0196US8298911B2Methods of forming wiring structuresLEE KYOUNG-WOO·Filed 2011·Granted Oct 30, 2012·39 cites·20 claims
- 0296US6856997B2Apparatus and method for providing file structure for multimedia streaming serviceLG ELECTRONICS INC·Filed 2001·Granted Feb 15, 2005·166 cites·18 claims
- 0395US6158017AMethod for storing parity and rebuilding data contents of failed disks in an external storage subsystem and apparatus thereofSAMSUNG ELECTRONICS CO LTD·Filed 1998·Granted Dec 5, 2000·198 cites·24 claims
- 0494US7911001B2Methods for forming self-aligned dual stress liners for CMOS semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Mar 22, 2011·29 cites·13 claims
- 0594US6861686B2Structure of a CMOS image sensor and method for fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Mar 1, 2005·103 cites·14 claims
- 0691US8232653B2Wiring structuresLEE KYOUNG-WOO·Filed 2010·Granted Jul 31, 2012·15 cites·7 claims
- 0791US7586175B2Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surfaceSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Sep 8, 2009·19 cites·14 claims
- 0890US7534678B2Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed therebySAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted May 19, 2009·20 cites·20 claims
- 0986US7205666B2Interconnections having double capping layer and method for forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Apr 17, 2007·10 cites·10 claims
- 1085US6828229B2Method of manufacturing interconnection line in semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Dec 7, 2004·33 cites·18 claims
- 1184US10229876B2Wiring structures and semiconductor devicesKIM JUN JUNG·Filed 2016·Granted Mar 12, 2019·9 cites·20 claims
- 1283US10825766B2Semiconductor device with multi-layered wiring and method for fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Nov 3, 2020·3 cites·14 claims
- 1383US7598168B2Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layerSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Oct 6, 2009·9 cites·25 claims
- 1480US7687915B2Semiconductor device having crack stop structureSAMSUNG ELECTRONICS CO LTD·Filed 2008·Granted Mar 30, 2010·9 cites·20 claims
- 1580US7387962B2Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallizationSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Jun 17, 2008·9 cites·14 claims
- 1680US6861347B2Method for forming metal wiring layer of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Mar 1, 2005·31 cites·54 claims
- 1778US8317826B2Absorbable bulky multi-filament draw textured yarn, manufacturing method thereof and medical use using themPARK YOUNG HWAN·Filed 2009·Granted Nov 27, 2012·6 cites·9 claims
- 1877US7781276B2Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilitiesSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Aug 24, 2010·4 cites·4 claims
- 1977US7605472B2Interconnections having double capping layer and method for forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Oct 20, 2009·5 cites·11 claims
- 2076US7323407B2Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base materialSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Jan 29, 2008·8 cites·43 claims
- 2176US7183195B2Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic fillerSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Feb 27, 2007·24 cites·51 claims
- 2275US6627540B2Method for forming dual damascene structure in semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2002·Granted Sep 30, 2003·22 cites·17 claims
- 2374US11078616B2Washing machineSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Aug 3, 2021·1 cites·8 claims
- 2474US7192864B2Method of forming interconnection lines for semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Mar 20, 2007·5 cites·16 claims
- 2573US8384131B2Semiconductor device and methods of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2008·Granted Feb 26, 2013·5 cites·21 claims
- 2673US6815331B2Method for forming metal wiring layer of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Nov 9, 2004·20 cites·17 claims
- 2772US10341981B2User terminal device and method for recognizing user'S location using sensor-based behavior recognitionSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jul 2, 2019·3 cites·13 claims
- 2872US7816271B2Methods for forming contacts for dual stress liner CMOS semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Oct 19, 2010·6 cites·18 claims
- 2972US7400003B2Structure of a CMOS image sensor and method for fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jul 15, 2008·12 cites·35 claims
- 3071US7800134B2CMOS integrated circuit devices having stressed NMOS and PMOS channel regions thereinSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted Sep 21, 2010·4 cites·7 claims
- 3171US7560332B2Integrated circuit capacitor structureSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jul 14, 2009·4 cites·14 claims
- 3271US7037835B2Interconnections having double capping layer and method for forming the sameSAMSUNG ELECRTONICS CO LTD·Filed 2003·Granted May 2, 2006·13 cites·17 claims
- 3370US9396988B2Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patternsLEE KYOUNG-WOO·Filed 2015·Granted Jul 19, 2016·2 cites·20 claims
- 3470US6953745B2Void-free metal interconnection structure and method of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Oct 11, 2005·17 cites·20 claims
- 3568US8697455B2Monitoring test element groups (TEGs) for etching process and methods of manufacturing a semiconductor device using the sameLEE KYOUNG-WOO·Filed 2012·Granted Apr 15, 2014·2 cites·20 claims
- 3667US7435673B2Methods of forming integrated circuit devices having metal interconnect structures thereinSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Oct 14, 2008·4 cites·16 claims
- 3766US7635645B2Method for forming interconnection line in semiconductor device and interconnection line structureSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Dec 22, 2009·6 cites·6 claims
- 3866US7365025B2Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristicsSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted Apr 29, 2008·2 cites·11 claims
- 3966US7064059B2Method of forming dual damascene metal interconnection employing sacrificial metal oxide layerSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jun 20, 2006·12 cites·20 claims
- 4064US7279733B2Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Oct 9, 2007·10 cites·20 claims
- 4164US6855629B2Method for forming a dual damascene wiring pattern in a semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Feb 15, 2005·12 cites·18 claims
- 4263US7399700B2Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricatingSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Jul 15, 2008·2 cites·15 claims
- 4363US7157366B2Method of forming metal interconnection layer of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jan 2, 2007·12 cites·38 claims
- 4463US6849536B2Inter-metal dielectric patterns and method of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Feb 1, 2005·12 cites·28 claims
- 4562US7462507B2Structure of a CMOS image sensor and method for fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Dec 9, 2008·7 cites·12 claims
- 4660US7282451B2Methods of forming integrated circuit devices having metal interconnect layers thereinINFINEON TECHNOLOGIES AG·Filed 2005·Granted Oct 16, 2007·1 cites·26 claims
- 4760US7022600B2Method of forming dual damascene interconnection using low-k dielectric materialSAMSUNG ELECTRONICS CO LTD·Filed 2003·Granted Apr 4, 2006·10 cites·12 claims
- 4858US7417302B2Semiconductor device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Aug 26, 2008·1 cites·20 claims
- 4958US6936533B2Method of fabricating semiconductor devices having low dielectric interlayer insulation layerSAMSUNG ELECTRONICS CO LTD·Filed 2001·Granted Aug 30, 2005·6 cites·18 claims
- 5056US7951712B2Interconnections having double capping layer and method for forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2009·Granted May 31, 2011·0 cites·16 claims
Showing the top 50 of 78 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →