Inventor · disambiguated record
L. James Hwang
Also filed as: HWANG L JAMES
43 granted patents·1 pending application·1,305 citations·filing 1998–2021
98Inventor score
Top patents by PatentIndex Score
44 records- 0195US6457164B1Hetergeneous method for determining module placement in FPGAsXILINX INC·Filed 2000·Granted Sep 24, 2002·103 cites·17 claims
- 0294US10977018B1Development environment for heterogeneous devicesXILINX INC·Filed 2019·Granted Apr 13, 2021·17 cites·20 claims
- 0394US9880966B1Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuitXILINX INC·Filed 2015·Granted Jan 30, 2018·14 cites·20 claims
- 0494US9652570B1Automatic implementation of a customized system-on-chipXILINX INC·Filed 2015·Granted May 16, 2017·21 cites·20 claims
- 0594US8775986B1Software debugging of synthesized hardwareXILINX INC·Filed 2013·Granted Jul 8, 2014·22 cites·16 claims
- 0694US7383478B1Wireless dynamic boundary-scan topologies for fieldXILINX INC·Filed 2005·Granted Jun 3, 2008·34 cites·13 claims
- 0794US6941538B2Method and system for integrating cores in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2002·Granted Sep 6, 2005·87 cites·13 claims
- 0893US8762916B1Automatic generation of a data transfer networkXILINX INC·Filed 2013·Granted Jun 24, 2014·20 cites·20 claims
- 0993US7058921B1Method and system for resource allocation in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2002·Granted Jun 6, 2006·96 cites·30 claims
- 1092US9223921B1Compilation of HLL code with hardware accelerated functionsXILINX INC·Filed 2014·Granted Dec 29, 2015·18 cites·20 claims
- 1192US7739092B1Fast hardware co-simulation reset using partial bitstreamsXILINX INC·Filed 2006·Granted Jun 15, 2010·38 cites·17 claims
- 1291US8024678B1Interfacing with a dynamically configurable arithmetic unitXILINX INC·Filed 2009·Granted Sep 20, 2011·22 cites·16 claims
- 1390US9147024B1Hardware and software cosynthesis performance estimationXILINX INC·Filed 2014·Granted Sep 29, 2015·14 cites·20 claims
- 1490US7085702B1Method and system for modeling and automatically generating an embedded system from a system-level environmentXILINX INC·Filed 2002·Granted Aug 1, 2006·55 cites·16 claims
- 1588US9805152B1Compilation of system designsXILINX INC·Filed 2016·Granted Oct 31, 2017·6 cites·20 claims
- 1688US6883147B1Method and system for generating a circuit design including a peripheral component connected to a busXILINX INC·Filed 2002·Granted Apr 19, 2005·52 cites·14 claims
- 1785US7523434B1Interfacing with a dynamically configurable arithmetic unitXILINX INC·Filed 2005·Granted Apr 21, 2009·14 cites·9 claims
- 1882US6216258B1FPGA modules parameterized by expressionsXILINX INC·Filed 1998·Granted Apr 10, 2001·84 cites·20 claims
- 1981US7216328B2Method and system for integrating cores in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2005·Granted May 8, 2007·9 cites·9 claims
- 2081US7003751B1Specification of the hierarchy, connectivity, and graphical representation of a circuit designXILINX INC·Filed 2003·Granted Feb 21, 2006·31 cites·23 claims
- 2180US6292925B1Context-sensitive self implementing modulesXILINX INC·Filed 1998·Granted Sep 18, 2001·90 cites·37 claims
- 2279US8868396B1Verification and debugging using heterogeneous simulation modelsSHIRAZI NABEEL·Filed 2009·Granted Oct 21, 2014·10 cites·15 claims
- 2379US7110935B1Method and system for modeling and automatically generating an electronic design from a system level environmentXILINX INC·Filed 2001·Granted Sep 19, 2006·29 cites·11 claims
- 2478US7203632B2HDL co-simulation in a high-level modeling systemXILINX INC·Filed 2003·Granted Apr 10, 2007·25 cites·22 claims
- 2578US6243851B1Heterogeneous method for determining module placement in FPGAsXILINX INC·Filed 1998·Granted Jun 5, 2001·71 cites·30 claims
- 2677US10635769B1Hardware and software event tracing for a system-on-chipXILINX INC·Filed 2015·Granted Apr 28, 2020·3 cites·19 claims
- 2776US11188312B2Hardware-software design flow with high-level synthesis for heterogeneous and programmable devicesXILINX INC·Filed 2019·Granted Nov 30, 2021·2 cites·18 claims
- 2876US7509614B2Method and system for integrating cores in FPGA-based system-on-chip (SoC)XILINX INC·Filed 2005·Granted Mar 24, 2009·6 cites·12 claims
- 2976US7433813B1Embedding a co-simulated hardware object in an event-driven simulatorXILINX INC·Filed 2004·Granted Oct 7, 2008·21 cites·22 claims
- 3075US6260182B1Method for specifying routing in a logic module by direct module communicationXILINX INC·Filed 1998·Granted Jul 10, 2001·70 cites·32 claims
- 3174US7934185B1Method of simulating bidirectional signals in a modeling systemXILINX INC·Filed 2008·Granted Apr 26, 2011·5 cites·20 claims
- 3273US7895584B1Translation of a program in a dynamically-typed language to a program in a hardware description languageXILINX INC·Filed 2003·Granted Feb 22, 2011·18 cites·13 claims
- 3372US7284225B1Embedding a hardware object in an application systemXILINX INC·Filed 2004·Granted Oct 16, 2007·17 cites·15 claims
- 3472US7194705B1Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptionsXILINX INC·Filed 2003·Granted Mar 20, 2007·19 cites·23 claims
- 3569US6408422B1Method for remapping logic modules to resources of a programmable gate arrayXILINX INC·Filed 1999·Granted Jun 18, 2002·44 cites·21 claims
- 3666US11645053B2Hardware-software design flow with high-level synthesis for heterogeneous and programmable devicesXILINX INC·Filed 2021·Granted May 9, 2023·0 cites·20 claims
- 3763US7363600B1Method of simulating bidirectional signals in a modeling systemXILINX INC·Filed 2003·Granted Apr 22, 2008·7 cites·18 claims
- 3862US7684968B1Generation of a high-level simulation model of an electronic system by combining an HDL control function translated to a high-level language and a separate high-level data path functionXILINX INC·Filed 2004·Granted Mar 23, 2010·10 cites·14 claims
- 3962US7478030B1Clock stabilization detection for hardware simulationXILINX INC·Filed 2003·Granted Jan 13, 2009·8 cites·24 claims
- 4062US6237129B1Method for constraining circuit element positions in structured layoutsXILINX INC·Filed 1998·Granted May 22, 2001·34 cites·35 claims
- 4159US6839879B1Method and system for time-stamping and managing electronic documentsXILINX INC·Filed 1999·Granted Jan 4, 2005·33 cites·21 claims
- 4256US7437280B1Hardware-based co-simulation on a PLD having an embedded processorXILINX INC·Filed 2004·Granted Oct 14, 2008·4 cites·11 claims
- 4349US6430732B1Method for structured layout in a hardware description languageXILINX INC·Filed 1999·Granted Aug 6, 2002·22 cites·3 claims
- 4443US2001001881A1Methods and media for utilizing symbolic expressions in circuit modulesFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →