Inventor · disambiguated record
Lawrence Lee Aldrich
Also filed as: ALDRICH LAWRENCE L · ALDRICH LAWRENCE LEE
3 granted patents·133 citations·filing 2000–2001
73Inventor score
Top patents by PatentIndex Score
3 records- 0190US6566720B2Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuitsUNITED MEMORIES INC·Filed 2001·Granted May 20, 2003·117 cites·17 claims
- 0270US6339541B1Architecture for high speed memory circuit having a relatively large number of internal data linesUNITED MEMORIES INC·Filed 2000·Granted Jan 15, 2002·14 cites·40 claims
- 0346US6266266B1Integrated circuit design exhibiting reduced capacitanceMOSEL VITELIC INC·Filed 2000·Granted Jul 24, 2001·2 cites·30 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →