Inventor · disambiguated record
Lakshminarayana B. Arimilli
Also filed as: ARIMILLI LAKSHMINARAYANA · ARIMILLI LAKSHMINARAYANA B · ARIMILLI LAKSHMINARAYANA BABA
130 granted patents·5 pending applications·2,065 citations·filing 1999–2020
99Inventor score
Top patents by PatentIndex Score
135 records- 0197US7840703B2System and method for dynamically supporting indirect routing within a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Nov 23, 2010·68 cites·17 claims
- 0295US10761995B2Integrated circuit and data processing system having a configurable cache directory for an acceleratorIBM·Filed 2019·Granted Sep 1, 2020·11 cites·20 claims
- 0395US9342387B1Hardware-assisted interthread push communicationIBM·Filed 2015·Granted May 17, 2016·13 cites·6 claims
- 0495US8108545B2Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architectureARIMILLI LAKSHMINARAYANA B·Filed 2007·Granted Jan 31, 2012·43 cites·20 claims
- 0593US9715470B1Direct memory access between an accelerator and a processor using a coherency adapterIBM·Filed 2016·Granted Jul 25, 2017·9 cites·20 claims
- 0692US9286148B1Hardware-assisted interthread push communicationIBM·Filed 2014·Granted Mar 15, 2016·13 cites·13 claims
- 0792US7958183B2Performing collective operations using software setup and partial software execution at leaf nodes in a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Jun 7, 2011·31 cites·20 claims
- 0891US8014387B2Providing a fully non-blocking switch in a supernode of a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Sep 6, 2011·22 cites·15 claims
- 0990US8234652B2Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasksARIMILLI LAKSHMINARAYANA B·Filed 2007·Granted Jul 31, 2012·20 cites·17 claims
- 1090US8077602B2Performing dynamic request routing based on broadcast queue depthsARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Dec 13, 2011·23 cites·21 claims
- 1189US8127300B2Hardware based dynamic load balancing of message passing interface tasksARIMILLI LAKSHMINARAYANA B·Filed 2007·Granted Feb 28, 2012·21 cites·17 claims
- 1288US10216653B2Pre-transmission data reordering for a serial interfaceIBM·Filed 2017·Granted Feb 26, 2019·5 cites·19 claims
- 1388US8185896B2Method for data processing using a multi-tiered full-graph interconnect architectureARIMILLI LAKSHMINARAYANA B·Filed 2007·Granted May 22, 2012·19 cites·24 claims
- 1487US8108876B2Modifying an operation of one or more processors executing message passing interface tasksARIMILLI LAKSHMINARAYANA B·Filed 2007·Granted Jan 31, 2012·17 cites·18 claims
- 1587US7779148B2Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chipsIBM·Filed 2008·Granted Aug 17, 2010·15 cites·18 claims
- 1686US7877436B2Mechanism to provide reliability through packet drop detectionIBM·Filed 2008·Granted Jan 25, 2011·15 cites·19 claims
- 1785US8484307B2Host fabric interface (HFI) to perform global shared memory (GSM) operationsARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Jul 9, 2013·15 cites·11 claims
- 1884US9575825B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Feb 21, 2017·6 cites·10 claims
- 1984US8122132B2Techniques for dynamically assigning jobs to processors in a cluster based on broadcast informationARIMILLI LAKSHMINARAYANA BABA·Filed 2008·Granted Feb 21, 2012·13 cites·20 claims
- 2084US7822889B2Direct/indirect transmission of information using a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Oct 26, 2010·13 cites·14 claims
- 2183US8312464B2Hardware based dynamic load balancing of message passing interface tasks by modifying tasksARIMILLI LAKSHMINARAYANA B·Filed 2007·Granted Nov 13, 2012·12 cites·16 claims
- 2283US7958309B2Dynamic selection of a memory access sizeIBM·Filed 2008·Granted Jun 7, 2011·12 cites·15 claims
- 2382US6393528B1Optimized cache allocation algorithm for multiple speculative requestsIBM·Filed 1999·Granted May 21, 2002·97 cites·21 claims
- 2481US10169247B2Direct memory access between an accelerator and a processor using a coherency adapterIBM·Filed 2017·Granted Jan 1, 2019·2 cites·20 claims
- 2581US8281075B2Processor system and methods of triggering a block move using a system bus write command initiated by user codeARIMILLI LAKSHMINARAYANA BABA·Filed 2009·Granted Oct 2, 2012·10 cites·20 claims
- 2681US6434669B1Method of cache management to dynamically update information-type dependent cache policiesIBM·Filed 1999·Granted Aug 13, 2002·95 cites·23 claims
- 2781US6356980B1Method and system for bypassing cache levels when casting out from an upper level cacheIBM·Filed 1999·Granted Mar 12, 2002·90 cites·20 claims
- 2880US8214424B2User level message broadcast mechanism in distributed computing environmentARIMILLI LAKSHMINARAYANA B·Filed 2009·Granted Jul 3, 2012·10 cites·20 claims
- 2980US7873879B2Mechanism to perform debugging of global shared memory (GSM) operationsIBM·Filed 2008·Granted Jan 18, 2011·10 cites·19 claims
- 3080US7797588B2Mechanism to provide software guaranteed reliability for GSM operationsIBM·Filed 2008·Granted Sep 14, 2010·10 cites·20 claims
- 3179US8108619B2Cache management for partial cache line operationsARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Jan 31, 2012·9 cites·15 claims
- 3279US7769892B2System and method for handling indirect routing of information between supernodes of a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Aug 3, 2010·8 cites·17 claims
- 3377US11113204B2Translation invalidation in a translation cache serving an acceleratorIBM·Filed 2019·Granted Sep 7, 2021·1 cites·20 claims
- 3477US10394711B2Managing lowest point of coherency (LPC) memory using a service layer adapterIBM·Filed 2016·Granted Aug 27, 2019·2 cites·20 claims
- 3577US6473833B1Integrated cache and directory structure for multi-level cachesIBM·Filed 1999·Granted Oct 29, 2002·76 cites·8 claims
- 3677US6408362B1Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached dataIBM·Filed 1999·Granted Jun 18, 2002·76 cites·21 claims
- 3776US8024527B2Partial cache line accesses based on memory access patternsIBM·Filed 2008·Granted Sep 20, 2011·7 cites·20 claims
- 3876US6345342B1Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache lineIBM·Filed 1999·Granted Feb 5, 2002·75 cites·16 claims
- 3976US6282615B1Multiprocessor system bus with a data-less castout mechanismIBM·Filed 1999·Granted Aug 28, 2001·69 cites·10 claims
- 4074US9892061B1Direct memory access between an accelerator and a processor using a coherency adapterIBM·Filed 2017·Granted Feb 13, 2018·1 cites·20 claims
- 4173US7769891B2System and method for providing multiple redundant direct routes between supernodes of a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Aug 3, 2010·5 cites·17 claims
- 4273US6633838B1Multi-state logic analyzer integral to a microprocessorIBM·Filed 1999·Granted Oct 14, 2003·64 cites·18 claims
- 4372US9766890B2Non-serialized push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Sep 19, 2017·2 cites·14 claims
- 4472US9678812B2Addressing for inter-thread push communicationIBM·Filed 2014·Granted Jun 13, 2017·2 cites·12 claims
- 4572US8417778B2Collective acceleration unit tree flow control and retransmitARIMILLI LAKSHMINARAYANA B·Filed 2009·Granted Apr 9, 2013·5 cites·19 claims
- 4671US8893148B2Performing setup operations for receiving different amounts of data while processors are performing message passing interface tasksARIMILLI LAKSHMINARAYANA B·Filed 2012·Granted Nov 18, 2014·2 cites·20 claims
- 4771US6425058B1Cache management mechanism to enable information-type dependent cache policiesIBM·Filed 1999·Granted Jul 23, 2002·50 cites·13 claims
- 4870US6535939B1Dynamically configurable memory bus and scalability ports via hardware monitored bus utilizationsIBM·Filed 1999·Granted Mar 18, 2003·56 cites·21 claims
- 4970US6405290B1Multiprocessor system bus protocol for O state memory-consistent dataIBM·Filed 1999·Granted Jun 11, 2002·55 cites·24 claims
- 5069US8255913B2Notification to task of completion of GSM operations by initiator nodeARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Aug 28, 2012·4 cites·12 claims
Showing the top 50 of 135 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →