Inventor · disambiguated record
Lap Chan
Also filed as: CHAN LAP · CHAN LAP HUNG · LEE JAMES YONG MENG
127 granted patents·5 pending applications·5,148 citations·filing 1996–2021
99Inventor score
Files withCHARTERED SEMICONDUCTOR MFG122UNIV SINGAPORE2CHARTERED SEMICONDUCTOR MANU L1CHARTERED SEMICONDUCTOR MFG CO1CHARTERED SEMICONDUCTORS MANUF1
Top patents by PatentIndex Score
132 records- 0198US6303418B1Method of fabricating CMOS devices featuring dual gate structures and a high dielectric constant gate insulator layerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 16, 2001·374 cites·28 claims
- 0297US8053340B2Method for fabricating semiconductor devices with reduced junction diffusionUNIV SINGAPORE·Filed 2007·Granted Nov 8, 2011·97 cites·26 claims
- 0397US6300177B1Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 9, 2001·175 cites·26 claims
- 0497US6136693AMethod for planarized interconnect vias using electroless plating and CMPCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Oct 24, 2000·289 cites·34 claims
- 0597US5870121ATi/titanium nitride and ti/tungsten nitride thin film resistors for thermal ink jet technologyCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Feb 9, 1999·140 cites·12 claims
- 0696US6461900B1Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 8, 2002·141 cites·22 claims
- 0796US6348385B1Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constantCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 19, 2002·128 cites·12 claims
- 0896US6261935B1Method of forming contact to polysilicon gate for MOS devicesCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 17, 2001·216 cites·28 claims
- 0995US5856225ACreation of a self-aligned, ion implanted channel region, after source and drain formationCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Jan 5, 1999·253 cites·22 claims
- 1094US6747314B2Method to form a self-aligned CMOS inverter using vertical device integrationCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Jun 8, 2004·93 cites·11 claims
- 1194US6313008B1Method to form a balloon shaped STI using a micro machining technique to remove heavily doped siliconCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 6, 2001·90 cites·30 claims
- 1291US6406945B1Method for forming a transistor gate dielectric with high-K and low-K regionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 18, 2002·59 cites·17 claims
- 1391US6403485B1Method to form a low parasitic capacitance pseudo-SOI CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·66 cites·27 claims
- 1491US6252277B1Embedded polysilicon gate MOSFETCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 26, 2001·137 cites·28 claims
- 1590US7570144B2Integrated transformer and method of fabrication thereofCHARTERED SEMICONDUCTOR MFG·Filed 2007·Granted Aug 4, 2009·24 cites·32 claims
- 1690US6468906B1Passivation of copper interconnect surfaces with a passivating metal layerCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Oct 22, 2002·67 cites·17 claims
- 1790US6252290B1Method to form, and structure of, a dual damascene interconnect deviceCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jun 26, 2001·123 cites·19 claims
- 1890US6121130ALaser curing of spin-on dielectric thin filmsCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Sep 19, 2000·118 cites·20 claims
- 1989US6417056B1Method to form low-overlap-capacitance transistors by forming microtrench at the gate edgeCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jul 9, 2002·51 cites·27 claims
- 2089US6319767B1Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Nov 20, 2001·50 cites·29 claims
- 2189US6306715B1Method to form smaller channel with CMOS device by isotropic etching of the gate materialsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 23, 2001·46 cites·14 claims
- 2288US6716693B1Method of forming a surface coating layer within an opening within a body by atomic layer depositionCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Apr 6, 2004·49 cites·28 claims
- 2388US6511884B1Method to form and/or isolate vertical transistorsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jan 28, 2003·48 cites·27 claims
- 2488US6468877B1Method to form an air-gap under the edges of a gate electrode by using disposable spacer/linerCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Oct 22, 2002·53 cites·21 claims
- 2587US6903013B2Method to fill a trench and tunnel by using ALD seed layer and electroless platingCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Jun 7, 2005·44 cites·54 claims
- 2687US6436770B1Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 20, 2002·45 cites·19 claims
- 2787US6387747B1Method to fabricate RF inductors with minimum areaCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 14, 2002·57 cites·29 claims
- 2887US6275089B1Low voltage controllable transient trigger network for ESD protectionCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Aug 14, 2001·45 cites·10 claims
- 2987US6110787AMethod for fabricating a MOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 29, 2000·99 cites·24 claims
- 3087US6100195APassivation of copper interconnect surfaces with a passivating metal layerCHARTERED SEMICONDUCTOR MANU L·Filed 1998·Granted Aug 8, 2000·122 cites·18 claims
- 3186US6355563B1Versatile copper-wiring layout design with low-k dielectric integrationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Mar 12, 2002·46 cites·33 claims
- 3285US11802370B2Method for decolorizing textilesHONG KONG RES INST TEXTILES & APPAREL LTD·Filed 2021·Granted Oct 31, 2023·2 cites·5 claims
- 3385US6001706AMethod for making improved shallow trench isolation for semiconductor integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Dec 14, 1999·103 cites·20 claims
- 3484US6204137B1Method to form transistors and local interconnects using a silicon nitride dummy gate techniqueCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Mar 20, 2001·44 cites·20 claims
- 3583US6709934B2Method for forming variable-K gate dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Mar 23, 2004·26 cites·10 claims
- 3682US6638844B1Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fillCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Oct 28, 2003·29 cites·70 claims
- 3782US6495200B1Method to deposit a seeding layer for electroless copper platingCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Dec 17, 2002·77 cites·16 claims
- 3882US6140237ADamascene process for forming coplanar top surface of copper connector isolated by barrier layers in an insulating layerCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 31, 2000·68 cites·27 claims
- 3981US6221727B1Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technologyCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Apr 24, 2001·66 cites·26 claims
- 4079US6214728B1Method to encapsulate copper plug for interconnect metallizationCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Apr 10, 2001·52 cites·20 claims
- 4179US6180501B1Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide processCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jan 30, 2001·44 cites·21 claims
- 4278US8354321B2Method for fabricating semiconductor devices with reduced junction diffusionGLOBALFOUNDRIES SG PTE LTD·Filed 2011·Granted Jan 15, 2013·4 cites·20 claims
- 4378US7573081B2Method to fabricate horizontal air columns underneath metal inductorCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Aug 11, 2009·7 cites·6 claims
- 4478US7030451B2Method and apparatus for performing nickel salicidationCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Apr 18, 2006·5 cites·10 claims
- 4578US6403484B1Method to achieve STI planarizationCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 11, 2002·23 cites·20 claims
- 4678US5858870AMethods for gap fill and planarization of intermetal dielectricsCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Jan 12, 1999·66 cites·18 claims
- 4777US6501122B1Flash device having a large planar area ono interpoly dielectricCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Dec 31, 2002·20 cites·19 claims
- 4877US6177324B1ESD protection device for STI deep submicron technologyCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jan 23, 2001·42 cites·24 claims
- 4976US7932152B2Method of forming a gate stack structureCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Apr 26, 2011·8 cites·25 claims
- 5076US6835631B1Method to enhance inductor Q factor by forming air gaps below inductorsCHARTERED SEMICONDUCTOR MFG·Filed 2003·Granted Dec 28, 2004·26 cites·63 claims
Showing the top 50 of 132 patent records by PatentIndex Score.
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