Inventor · disambiguated record
Lawrence F. Childs
Also filed as: CHILDS LAWRENCE F
11 granted patents·1 pending application·470 citations·filing 1994–2010
93Inventor score
Top patents by PatentIndex Score
12 records- 0196US5440514AWrite control for a memory using a delay locked loopMOTOROLA INC·Filed 1994·Granted Aug 8, 1995·150 cites·21 claims
- 0292US5384737APipelined memory having synchronous and asynchronous operating modesMOTOROLA INC·Filed 1994·Granted Jan 24, 1995·95 cites·20 claims
- 0391US5477176APower-on reset circuit for preventing multiple word line selections during power-up of an integrated circuit memoryMOTOROLA INC·Filed 1994·Granted Dec 19, 1995·73 cites·19 claims
- 0488US7800959B2Memory having self-timed bit line boost circuit and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Sep 21, 2010·23 cites·20 claims
- 0584US7940599B2Dual port memory deviceFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted May 10, 2011·18 cites·18 claims
- 0679US7746716B2Memory having a dummy bitline for timing controlFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Jun 29, 2010·13 cites·20 claims
- 0779US7292485B1SRAM having variable power supply and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 6, 2007·13 cites·20 claims
- 0872US5400274AMemory having looped global data lines for propagation delay matchingMOTOROLA INC·Filed 1994·Granted Mar 21, 1995·32 cites·17 claims
- 0968US5426381ALatching ECL to CMOS input buffer circuitMOTOROLA INC·Filed 1994·Granted Jun 20, 1995·21 cites·20 claims
- 1056US5670815ALayout for noise reduction on a reference voltageMOTOROLA INC·Filed 1994·Granted Sep 23, 1997·25 cites·11 claims
- 1140US5416744AMemory having bit line load with automatic bit line precharge and equalizationMOTOROLA INC·Filed 1994·Granted May 16, 1995·7 cites·17 claims
- 1231US2011128807A1Memory device and sense circuitry thereforFREESCALE SEMICONDUCTOR INC·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →