Inventor · disambiguated record
Lap-Wai Chow
Also filed as: CHOW LAP W · CHOW LAP-WAI
64 granted patents·4 pending applications·1,814 citations·filing 1994–2021
99Inventor score
Top patents by PatentIndex Score
68 records- 0199US5991209ASplit sense amplifier and staging buffer for wide memory architectureRAYTHEON CO·Filed 1997·Granted Nov 23, 1999·421 cites·17 claims
- 0297US8111089B2Building block for a secure CMOS logic cell libraryCOCCHI RONALD P·Filed 2010·Granted Feb 7, 2012·34 cites·19 claims
- 0396US6396368B1CMOS-compatible MEM switches and method of makingHRL LAB LLC·Filed 1999·Granted May 28, 2002·93 cites·19 claims
- 0492US7344932B2Use of silicon block process step to camouflage a false transistorHRL LAB LLC·Filed 2005·Granted Mar 18, 2008·19 cites·2 claims
- 0591US7008873B2Integrated circuit with reverse engineering protectionRAYTHEON CO·Filed 2005·Granted Mar 7, 2006·20 cites·14 claims
- 0691US6294816B1Secure integrated circuitHUGHES ELECTRONICS CORP·Filed 1998·Granted Sep 25, 2001·99 cites·1 claims
- 0791US5783846ADigital circuit with transistor geometry and channel stops providing camouflage against reverse engineeringHUGHES ELECTRONICS CORP·Filed 1995·Granted Jul 21, 1998·102 cites·29 claims
- 0890US8510700B2Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processingCOCCHI RONALD P·Filed 2012·Granted Aug 13, 2013·8 cites·89 claims
- 0990US5866933AIntegrated circuit security system and method with implanted interconnectionsHUGHES ELECTRONICS CORP·Filed 1994·Granted Feb 2, 1999·94 cites·16 claims
- 1089US6117762AMethod and apparatus using silicide layer for protecting integrated circuits from reverse engineeringHRL LAB LLC·Filed 1999·Granted Sep 12, 2000·75 cites·11 claims
- 1188US9735781B2Physically unclonable camouflage structure and methods for fabricating sameSYPHERMEDIA INT INC·Filed 2015·Granted Aug 15, 2017·5 cites·17 claims
- 1288US8151235B2Camouflaging a standard cell based integrated circuitCHOW LAP WAI·Filed 2009·Granted Apr 3, 2012·19 cites·36 claims
- 1388US5930663ADigital circuit with transistor geometry and channel stops providing camouflage against reverse engineeringHUGHES ELECTRONICS CORP·Filed 1998·Granted Jul 27, 1999·75 cites·9 claims
- 1487US8095993B2Cryptographic architecture with instruction masking and other techniques for thwarting differential power analysisSHU DAVID B·Filed 2005·Granted Jan 10, 2012·13 cites·10 claims
- 1587US6667245B2CMOS-compatible MEM switches and method of makingHRL LAB LLC·Filed 2001·Granted Dec 23, 2003·62 cites·14 claims
- 1686US6613661B1Process for fabricating secure integrated circuitHUGHES ELECTRONICS CORP·Filed 2000·Granted Sep 2, 2003·35 cites·11 claims
- 1786US6064110ADigital circuit with transistor geometry and channel stops providing camouflage against reverse engineeringHUGHES ELECTRONICS CORP·Filed 1999·Granted May 16, 2000·65 cites·12 claims
- 1884US6791191B2Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminationsHRL LAB LLC·Filed 2001·Granted Sep 14, 2004·38 cites·21 claims
- 1984US6740942B2Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contactHRL LAB LLC·Filed 2001·Granted May 25, 2004·49 cites·19 claims
- 2084US5973375ACamouflaged circuit structure with step implantsHUGHES ELECTRONICS CORP·Filed 1997·Granted Oct 26, 1999·76 cites·32 claims
- 2183US6815816B1Implanted hidden interconnections in a semiconductor device for preventing reverse engineeringHRL LAB LLC·Filed 2000·Granted Nov 9, 2004·31 cites·22 claims
- 2283US6459629B1Memory with a bit line block and/or a word line block for preventing reverse engineeringHRL LAB LLC·Filed 2001·Granted Oct 1, 2002·27 cites·23 claims
- 2382US7049667B2Conductive channel pseudo block process and circuit to inhibit reverse engineeringRAYTHEON CO·Filed 2003·Granted May 23, 2006·25 cites·5 claims
- 2482US6924552B2Multilayered integrated circuit with extraneous conductive tracesPROMTEK·Filed 2003·Granted Aug 2, 2005·42 cites·48 claims
- 2581US10574237B2Physically unclonable camouflage structure and methods for fabricating sameSYPHERMEDIA INT INC·Filed 2017·Granted Feb 25, 2020·2 cites·46 claims
- 2681US6897535B2Integrated circuit with reverse engineering protectionHRL LAB LLC·Filed 2003·Granted May 24, 2005·26 cites·22 claims
- 2779US10817638B2Method and apparatus for camouflaging an integrated circuit using virtual camouflage cellsINSIDE SECURE·Filed 2019·Granted Oct 27, 2020·2 cites·21 claims
- 2879US8258583B1Conductive channel pseudo block process and circuit to inhibit reverse engineeringCHOW LAP-WAI·Filed 2010·Granted Sep 4, 2012·4 cites·16 claims
- 2979US8168487B2Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineerCLARK JR WILLIAM M·Filed 2007·Granted May 1, 2012·9 cites·3 claims
- 3078US7242063B1Symmetric non-intrusive and covert technique to render a transistor permanently non-operableHRL LAB LLC·Filed 2004·Granted Jul 10, 2007·22 cites·16 claims
- 3178US6979606B2Use of silicon block process step to camouflage a false transistorRAYTHEON CO·Filed 2003·Granted Dec 27, 2005·19 cites·4 claims
- 3277US7935603B1Symmetric non-intrusive and covert technique to render a transistor permanently non-operableHRL LAB LLC·Filed 2007·Granted May 3, 2011·6 cites·15 claims
- 3377US6774413B2Integrated circuit structure with programmable connector/isolatorHRL LAB LLC·Filed 2001·Granted Aug 10, 2004·21 cites·8 claims
- 3475US6893916B2Programmable connector/isolator and double polysilicon layer CMOS process with buried contact using the sameHRL LAB LLC·Filed 2003·Granted May 17, 2005·18 cites·6 claims
- 3574US6940764B2Memory with a bit line block and/or a word line block for preventing reverse engineeringHRL LAB LLC·Filed 2002·Granted Sep 6, 2005·16 cites·23 claims
- 3672US7541266B2Covert transformation of transistor properties as a circuit protection methodHRL LAB LLC·Filed 2007·Granted Jun 2, 2009·4 cites·15 claims
- 3769US7166515B2Implanted hidden interconnections in a semiconductor device for preventing reverse engineeringHRL LAB LLC·Filed 2002·Granted Jan 23, 2007·13 cites·25 claims
- 3869US6919600B2Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contactHRL LAB LLC·Filed 2004·Granted Jul 19, 2005·20 cites·6 claims
- 3968US9940425B2Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processingSYPHERMEDIA INT INC·Filed 2016·Granted Apr 10, 2018·1 cites·33 claims
- 4067US8049281B1Symmetric non-intrusive and covert technique to render a transistor permanently non-operableHRL LAB LLC·Filed 2010·Granted Nov 1, 2011·2 cites·16 claims
- 4167US7949883B2Cryptographic CPU architecture with random instruction masking to thwart differential power analysisHRL LAB LLC·Filed 2004·Granted May 24, 2011·8 cites·29 claims
- 4266US11264990B2Physically unclonable camouflage structure and methods for fabricating sameRAMBUS INC·Filed 2020·Granted Mar 1, 2022·0 cites·20 claims
- 4365US8679908B1Use of silicide block process to camouflage a false transistorCHOW LAP-WAI·Filed 2007·Granted Mar 25, 2014·2 cites·17 claims
- 4465US7888213B2Conductive channel pseudo block process and circuit to inhibit reverse engineeringHRL LAB LLC·Filed 2006·Granted Feb 15, 2011·2 cites·16 claims
- 4565US7217977B2Covert transformation of transistor properties as a circuit protection methodHRL LAB LLC·Filed 2004·Granted May 15, 2007·10 cites·18 claims
- 4664US11163930B2Secure logic locking and configuration with camouflaged programmable micro netlistsRAMBUS INC·Filed 2020·Granted Nov 2, 2021·0 cites·20 claims
- 4764US8065532B2Cryptographic architecture with random instruction masking to thwart differential power analysisSHU DAVID B·Filed 2004·Granted Nov 22, 2011·6 cites·34 claims
- 4863US8418091B2Method and apparatus for camouflaging a standard cell based integrated circuitCHOW LAP WAI·Filed 2009·Granted Apr 9, 2013·2 cites·18 claims
- 4963US8296577B2Cryptographic bus architecture for the prevention of differential power analysisSHU DAVID B·Filed 2004·Granted Oct 23, 2012·6 cites·31 claims
- 5061US8564073B1Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineerCLARK JR WILLIAM M·Filed 2012·Granted Oct 22, 2013·1 cites·14 claims
Showing the top 50 of 68 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →