Inventor · disambiguated record
Lawrence D. Curley
Also filed as: CURLEY LAWRENCE D · CURLEY LAWRENCE DAVID
18 granted patents·404 citations·filing 1992–2016
94Inventor score
Top patents by PatentIndex Score
18 records- 0194US6714826B1Facility for simultaneously outputting both a mixed digital audio signal and an unmixed digital audio signal multiple concurrently received streams of digital audio dataIBM·Filed 2000·Granted Mar 30, 2004·142 cites·49 claims
- 0288US6519283B1Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphicsIBM·Filed 1999·Granted Feb 11, 2003·110 cites·21 claims
- 0387US9318171B2Dual asynchronous and synchronous memory systemIBM·Filed 2014·Granted Apr 19, 2016·8 cites·12 claims
- 0487US9142272B2Dual asynchronous and synchronous memory systemIBM·Filed 2013·Granted Sep 22, 2015·9 cites·8 claims
- 0577US5920359AVideo encoding method, system and computer program product for optimizing center of picture qualityIBM·Filed 1997·Granted Jul 6, 1999·58 cites·19 claims
- 0675US9563548B2Error injection and error counting during memory scrubbing operationsIBM·Filed 2015·Granted Feb 7, 2017·3 cites·7 claims
- 0775US8364904B2Horizontal cache persistence in a multi-compute node, symmetric multiprocessing computerIBM·Filed 2010·Granted Jan 29, 2013·4 cites·24 claims
- 0871US9459997B2Error injection and error counting during memory scrubbing operationsIBM·Filed 2014·Granted Oct 4, 2016·3 cites·13 claims
- 0970US7987400B2Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchyIBM·Filed 2008·Granted Jul 26, 2011·6 cites·18 claims
- 1067US7979732B2Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuitIBM·Filed 2007·Granted Jul 12, 2011·5 cites·17 claims
- 1164US6198772B1Motion estimation processor for a digital video encoderIBM·Filed 1997·Granted Mar 6, 2001·22 cites·12 claims
- 1258US6469743B1Programmable external graphics/video port for digital video decode system chipIBM·Filed 1999·Granted Oct 22, 2002·22 cites·25 claims
- 1351US9437327B2Combined rank and linear address incrementing utility for computer memory test operationsIBM·Filed 2016·Granted Sep 6, 2016·0 cites·1 claims
- 1448US7979838B2Method of automating creation of a clock control distribution network in an integrated circuit floorplanIBM·Filed 2008·Granted Jul 12, 2011·0 cites·12 claims
- 1544US9298614B2Combined rank and linear address incrementing utility for computer memory test operationsIBM·Filed 2014·Granted Mar 29, 2016·0 cites·20 claims
- 1643US8688880B2Centralized serialization of requests in a multiprocessor systemDRAPALA GARRETT M·Filed 2010·Granted Apr 1, 2014·0 cites·20 claims
- 1739US8479070B2Integrated circuit arrangement for test inputsBAUR ULRICH·Filed 2010·Granted Jul 2, 2013·0 cites·16 claims
- 1838US5309037APower-on reset circuit with arbitrary output preventionIBM·Filed 1992·Granted May 3, 1994·12 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →