Inventor · disambiguated record
Laique Khan
Also filed as: KHAN LAIQUE
3 granted patents·119 citations·filing 1996–1996
75Inventor score
Files withLSI LOGIC CORP3
Top patents by PatentIndex Score
3 records- 0178US5963801AMethod of forming retrograde well structures and punch-through barriers using low energy implantsLSI LOGIC CORP·Filed 1996·Granted Oct 5, 1999·60 cites·14 claims
- 0277US5877530AFormation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantationLSI LOGIC CORP·Filed 1996·Granted Mar 2, 1999·44 cites·10 claims
- 0348US6180470B1FETs having lightly doped drain regions that are shaped with counter and noncounter dorant elementsLSI LOGIC CORP·Filed 1996·Granted Jan 30, 2001·15 cites·42 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →