Inventor · disambiguated record
Lavi Koch
Also filed as: KOCH LAVI
15 granted patents·3 pending applications·19 citations·filing 2008–2024
86Inventor score
Files withMELLANOX TECHNOLOGIES LTD11MELLANOX TECH TLV LTD4FREESCALE1FREESCALE SEMICONDUCTOR INC1MOSTINSKI ROMAN1
Top patents by PatentIndex Score
18 records- 0190US11283454B2Synthesized clock synchronization between network devicesMELLANOX TECHNOLOGIES LTD·Filed 2020·Granted Mar 22, 2022·3 cites·20 claims
- 0289US10778406B2Synthesized clock synchronization between networks devicesMELLANOX TECHNOLOGIES LTD·Filed 2018·Granted Sep 15, 2020·11 cites·18 claims
- 0384US10412673B2Power-efficient activation of multi-lane ports in a network elementMELLANOX TECH TLV LTD·Filed 2017·Granted Sep 10, 2019·4 cites·22 claims
- 0464US12294522B1Mitigating voltage surges in a network device by controlling port bandwidthsMELLANOX TECHNOLOGIES LTD·Filed 2023·Granted May 6, 2025·0 cites·20 claims
- 0560US12500830B2Link trainingMELLANOX TECHNOLOGIES LTD·Filed 2023·Granted Dec 16, 2025·0 cites·30 claims
- 0660US11637557B2Synthesized clock synchronization between network devicesMELLANOX TECHNOLOGIES LTD·Filed 2022·Granted Apr 25, 2023·0 cites·19 claims
- 0760US10915154B1Raising maximal silicon die temperature using reliability modelMELLANOX TECH TLV LTD·Filed 2019·Granted Feb 9, 2021·0 cites·35 claims
- 0856US12418393B2Power state management for fabricsMELLANOX TECHNOLOGIES LTD·Filed 2022·Granted Sep 16, 2025·0 cites·26 claims
- 0950US7688127B2Method for generating a output clock signal having a output cycle and a device having a clock signal generating capabilitiesFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Mar 30, 2010·0 cites·20 claims
- 1050US2025350300A1Estimating Long-Term Block Error Rate of a Forward Error Correction CodeMELLANOX TECHNOLOGIES LTD·Filed 2024·Application pending·0 cites
- 1148US10951545B2Network devicesMELLANOX TECH TLV LTD·Filed 2019·Granted Mar 16, 2021·0 cites·16 claims
- 1247US8706928B2Integrated circuit and method for reducing violations of a timing constraintMOSTINSKI ROMAN·Filed 2009·Granted Apr 22, 2014·0 cites·20 claims
- 1347US2025279926A1System for efficient link failure management using physical layer transmissionMELLANOX TECHNOLOGIES LTD·Filed 2024·Application pending·0 cites
- 1443US11349780B2Enhancing port link-up timeMELLANOX TECHNOLOGIES LTD·Filed 2020·Granted May 31, 2022·0 cites·19 claims
- 1543US10503682B1Accessing PCIe configuration data through networkMELLANOX TECHNOLOGIES LTD·Filed 2018·Granted Dec 10, 2019·0 cites·8 claims
- 1643US10324513B2Control of peripheral device data exchange based on CPU power stateMELLANOX TECHNOLOGIES LTD·Filed 2015·Granted Jun 18, 2019·0 cites·27 claims
- 1740US7786809B1Method of low power PLL for low jitter demanding applicationsFREESCALE·Filed 2008·Granted Aug 31, 2010·1 cites·20 claims
- 1838US2018199292A1Fabric Wise Width ReductionMELLANOX TECH TLV LTD·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →