Inventor · disambiguated record
Larry D. Larsen
Also filed as: LARSEN LARRY · LARSEN LARRY D · LARSEN LARRY DONALD
34 granted patents·1,529 citations·filing 1975–2014
98Inventor score
Top patents by PatentIndex Score
34 records- 0195US4027267AMethod of decoding data content of F2F and phase shift encoded data streamsIBM·Filed 1976·Granted May 31, 1977·115 cites·8 claims
- 0292US6397324B1Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register fileBOPS INC·Filed 2000·Granted May 28, 2002·79 cites·34 claims
- 0391US7493474B1Methods and apparatus for transforming, loading, and executing super-set instructionsALTERA CORP·Filed 2004·Granted Feb 17, 2009·59 cites·17 claims
- 0491US6557094B2Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsBOPS INC·Filed 2001·Granted Apr 29, 2003·48 cites·35 claims
- 0590US5682491ASelective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifierIBM·Filed 1994·Granted Oct 28, 1997·179 cites·21 claims
- 0688US6128720ADistributed processing array with component processors performing customized interpretation of instructionsIBM·Filed 1997·Granted Oct 3, 2000·167 cites·23 claims
- 0787US6321322B1Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsBOPS INC·Filed 2000·Granted Nov 20, 2001·35 cites·20 claims
- 0885US8489858B2Methods and apparatus for scalable array processor interrupt detection and responseBARRY EDWIN FRANKLIN·Filed 2012·Granted Jul 16, 2013·5 cites·20 claims
- 0985US5659722AMultiple condition code branching system in a multi-processor environmentIBM·Filed 1994·Granted Aug 19, 1997·110 cites·10 claims
- 1085US5115500APlural incompatible instruction format decode method and apparatusIBM·Filed 1988·Granted May 19, 1992·81 cites·7 claims
- 1184US6842811B2Methods and apparatus for scalable array processor interrupt detection and responsePTS CORP·Filed 2001·Granted Jan 11, 2005·24 cites·22 claims
- 1283US5649135AParallel processing system and method using surrogate instructionsIBM·Filed 1995·Granted Jul 15, 1997·116 cites·23 claims
- 1382US6101592AMethods and apparatus for scalable instruction set architecture with dynamic compact instructionsBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Aug 8, 2000·71 cites·12 claims
- 1480US7502451B2Institutional electronic messaging systemMICROWORKS INC·Filed 2006·Granted Mar 10, 2009·20 cites·32 claims
- 1580US4794517AThree phased pipelined signal processorIBM·Filed 1985·Granted Dec 27, 1988·69 cites·1 claims
- 1678US5659785AArray processor communication architecture with broadcast processor instructionsIBM·Filed 1995·Granted Aug 19, 1997·97 cites·5 claims
- 1776USD247665SFire alarm housingPATENT DEVELOPMENT & MAN COMPANY·Filed 1976·Granted Apr 4, 1978·14 cites·1 claims
- 1875US7340591B1Providing parallel operand functions using register file and extra path storageALTERA CORP·Filed 2004·Granted Mar 4, 2008·20 cites·16 claims
- 1975US6848041B2Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsPTS CORP·Filed 2003·Granted Jan 25, 2005·15 cites·31 claims
- 2072US6408382B1Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architectureBOPS INC·Filed 1999·Granted Jun 18, 2002·54 cites·43 claims
- 2171US9158547B2Methods and apparatus for scalable array processor interrupt detection and responseBARRY EDWIN FRANKLIN·Filed 2014·Granted Oct 13, 2015·1 cites·20 claims
- 2270US7853779B2Methods and apparatus for scalable array processor interrupt detection and responseALTERA CORP·Filed 2008·Granted Dec 14, 2010·2 cites·23 claims
- 2366US5081574ABranch control in a three phase pipelined signal processorIBM·Filed 1990·Granted Jan 14, 1992·47 cites·1 claims
- 2463US4083037ADetection circuitPATENT DEV & MANAGEMENT·Filed 1975·Granted Apr 4, 1978·15 cites·21 claims
- 2562US7386710B2Methods and apparatus for scalable array processor interrupt detection and responseALTERA CORP·Filed 2004·Granted Jun 10, 2008·4 cites·9 claims
- 2660US5371872AMethod and apparatus for controlling operation of a cache memory during an interruptIBM·Filed 1991·Granted Dec 6, 1994·37 cites·27 claims
- 2758US8751772B2Methods and apparatus for scalable array processor interrupt detection and responseBARRY EDWIN FRANKLIN·Filed 2013·Granted Jun 10, 2014·0 cites·19 claims
- 2857USRE40509EMethods and apparatus for abbreviated instruction sets adaptable to configurable processor architectureALTERA CORP·Filed 2004·Granted Sep 16, 2008·4 cites·57 claims
- 2957US4246572ADetection circuit with hysteresisPATENT DEV & MANAGEMENT·Filed 1978·Granted Jan 20, 1981·13 cites·9 claims
- 3054US9672033B2Methods and apparatus for transforming, loading, and executing super-set instructionsPECHANEK GERALD GEORGE·Filed 2009·Granted Jun 6, 2017·0 cites·21 claims
- 3154US8161267B2Methods and apparatus for scalable array processor interrupt detection and responseBARRY EDWIN FRANKLIN·Filed 2010·Granted Apr 17, 2012·0 cites·19 claims
- 3253US4663675AApparatus and method for digital speech filing and retrievalIBM·Filed 1984·Granted May 5, 1987·9 cites·7 claims
- 3349US4691794AWeight scales and strain gauge assemblies useable thereinFYRNETICS INC·Filed 1983·Granted Sep 8, 1987·13 cites·62 claims
- 3442US4075487AIonization chamber assemblyPATENT DEV & MANAGEMENT·Filed 1976·Granted Feb 21, 1978·6 cites·56 claims
Join the waitlist — get patent alerts
Get an alert when Larry D. Larsen files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →