Inventor · disambiguated record
Larry Scott Leitner
Also filed as: LEITNER LARRY · LEITNER LARRY S · LEITNER LARRY SCOTT
20 granted patents·8 pending applications·340 citations·filing 1999–2023
94Inventor score
Top patents by PatentIndex Score
28 records- 0197US7343476B2Intelligent SMT thread hang detect taking into account shared resource contention/blockingIBM·Filed 2005·Granted Mar 11, 2008·82 cites·3 claims
- 0286US6393594B1Method and system for performing pseudo-random testing of an integrated circuitIBM·Filed 1999·Granted May 21, 2002·63 cites·17 claims
- 0383US6802031B2Method and apparatus for increasing the effectiveness of system debug and analysisIBM·Filed 2001·Granted Oct 5, 2004·38 cites·36 claims
- 0478US7725685B2Intelligent SMT thread hang detect taking into account shared resource contention/blockingIBM·Filed 2008·Granted May 25, 2010·8 cites·11 claims
- 0577US7657893B2Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processorIBM·Filed 2003·Granted Feb 2, 2010·18 cites·20 claims
- 0676US6857083B2Method and system for triggering a debugging unitIBM·Filed 2000·Granted Feb 15, 2005·23 cites·32 claims
- 0773US6633838B1Multi-state logic analyzer integral to a microprocessorIBM·Filed 1999·Granted Oct 14, 2003·64 cites·18 claims
- 0871US9003417B2Processor with resource usage counters for per-thread accountingARMSTRONG WILLIAM JOSEPH·Filed 2012·Granted Apr 7, 2015·2 cites·18 claims
- 0971US8271738B2Apparatus for operating cache-inhibited memory mapped commands to access registersFIELDS JR JAMES STEPHEN·Filed 2008·Granted Sep 18, 2012·6 cites·9 claims
- 1063US11301392B2Address translation cache invalidation in a microprocessorIBM·Filed 2020·Granted Apr 12, 2022·0 cites·20 claims
- 1163US7392350B2Method to operate cache-inhibited memory mapped commands to access registersIBM·Filed 2005·Granted Jun 24, 2008·2 cites·5 claims
- 1259US10915456B2Address translation cache invalidation in a microprocessorIBM·Filed 2019·Granted Feb 9, 2021·0 cites·25 claims
- 1356US8209698B2Processor core with per-thread resource usage accounting logicARMSTRONG WILLIAM JOSEPH·Filed 2009·Granted Jun 26, 2012·0 cites·13 claims
- 1455US11243864B2Identifying translation errorsIBM·Filed 2019·Granted Feb 8, 2022·0 cites·18 claims
- 1554US11080122B2Software-invisible interrupt for a microprocessorIBM·Filed 2019·Granted Aug 3, 2021·0 cites·8 claims
- 1651US7574581B2Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled componentsIBM·Filed 2003·Granted Aug 11, 2009·3 cites·7 claims
- 1748US7996703B2Method and apparatus to avoid power transients during a microprocessor testIBM·Filed 2008·Granted Aug 9, 2011·0 cites·14 claims
- 1847US8639855B2Information collection and storage for single core chips to 'N core chipsHARPER MICHAEL W·Filed 2008·Granted Jan 28, 2014·0 cites·19 claims
- 1947US6543003B1Method and apparatus for multi-stage hang recovery in an out-of-order microprocessorIBM·Filed 1999·Granted Apr 1, 2003·18 cites·44 claims
- 2046US2025149103A1Deterministic test program generation for evaluating cache coherencyIBM·Filed 2023·Application pending·0 cites
- 2144US2004216003A1Mechanism for FRU fault isolation in distributed nodal environmentIBM·Filed 2003·Application pending·0 cites
- 2243US2006184771A1Mini-refresh processor recovery as bug workaround method using existing recovery hardwareIBM·Filed 2005·Application pending·0 cites
- 2343US2006184770A1Method of implementing precise, localized hardware-error workarounds under centralized controlIBM·Filed 2005·Application pending·0 cites
- 2443US2006184769A1Localized generation of global flush requests while guaranteeing forward progress of a processorIBM·Filed 2005·Application pending·0 cites
- 2542US2006184840A1Using timebase register for system checkstop in clock running environment in a distributed nodal environmentIBM·Filed 2005·Application pending·0 cites
- 2641US6529979B1Method and apparatus for a high-speed serial communications bus protocol with positive acknowledgementIBM·Filed 1999·Granted Mar 4, 2003·13 cites·20 claims
- 2737US2006184832A1Method and apparatus for achieving high cycle/trace compression depth by adding widthIBM·Filed 2005·Application pending·0 cites
- 2836US2004216061A1Embeddable method and apparatus for functional pattern testing of repeatable program instruction-driven logic circuits via signal signature generationIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →