Inventor · disambiguated record
Larry A. Nesbit
Also filed as: NESBIT LARRY · NESBIT LARRY A · NESBIT LARRY ALLAN
10 granted patents·361 citations·filing 1981–2004
92Inventor score
Top patents by PatentIndex Score
10 records- 0192US4601779AMethod of producing a thin silicon-on-insulator layerIBM·Filed 1985·Granted Jul 22, 1986·123 cites·27 claims
- 0283US4532700AMethod of manufacturing semiconductor structures having an oxidized porous silicon isolation layerIBM·Filed 1984·Granted Aug 6, 1985·52 cites·15 claims
- 0381US5573633AMethod of chemically mechanically polishing an electronic componentIBM·Filed 1995·Granted Nov 12, 1996·56 cites·11 claims
- 0480US4558508AProcess of making dual well CMOS semiconductor structure with aligned field-dopings using single masking stepIBM·Filed 1984·Granted Dec 17, 1985·48 cites·7 claims
- 0576US7187085B2Semiconductor device including dual damascene interconnectionsIBM·Filed 2004·Granted Mar 6, 2007·19 cites·19 claims
- 0675US4389257AFabrication method for high conductivity, void-free polysilicon-silicide integrated circuit electrodesIBM·Filed 1981·Granted Jun 21, 1983·27 cites·15 claims
- 0771US6759332B2Method for producing dual damascene interconnections and structure produced therebyIBM·Filed 2001·Granted Jul 6, 2004·15 cites·24 claims
- 0860US7125790B2Inclusion of low-k dielectric material between bit linesINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 24, 2006·7 cites·23 claims
- 0952US6890815B2Reduced cap layer erosion for borderless contactsIBM·Filed 2003·Granted May 10, 2005·5 cites·25 claims
- 1042US5795826AMethod of chemically mechanically polishing an electronic componentIBM·Filed 1996·Granted Aug 18, 1998·9 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →