Inventor · disambiguated record
Lakshmipriya Seshan
Also filed as: SESHAN LAKSHMIPRIYA
15 granted patents·9 pending applications·24 citations·filing 2019–2025
87Inventor score
Top patents by PatentIndex Score
24 records- 0193US12360934B2Parameter exchange for a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 15, 2025·2 cites·20 claims
- 0291US12332826B2Die-to-die interconnectINTEL CORP·Filed 2022·Granted Jun 17, 2025·2 cites·20 claims
- 0391US10686582B1Clock phase compensation apparatus and methodINTEL CORP·Filed 2019·Granted Jun 16, 2020·17 cites·21 claims
- 0487US12481614B2Standard interfaces for die to die (D2D) interconnect stacksINTEL CORP·Filed 2022·Granted Nov 25, 2025·1 cites·20 claims
- 0587US12353305B2Compliance and debug testing of a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 8, 2025·1 cites·20 claims
- 0679US2025370945A1Optimized transmission of priority packets via universal chiplet interconnect express (ucie) sideband linkCHOUDHARY SWADESH·Filed 2025·Application pending·0 cites
- 0777US12117960B2Approximate data bus inversion technique for latency sensitive applicationsINTEL CORP·Filed 2020·Granted Oct 15, 2024·1 cites·20 claims
- 0873US2025123989A1Optimized transmission and broadcasting of priority packets and critical events via ucie-sidebandCHOUDHARY SWADESH·Filed 2024·Application pending·0 cites
- 0963US11971841B2Link layer-PHY interface adapterINTEL CORP·Filed 2020·Granted Apr 30, 2024·0 cites·20 claims
- 1061US12499019B2Retimers to extend a die-to-die interconnectINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 1160US12362306B2Clock-gating in die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Jul 15, 2025·0 cites·20 claims
- 1258US12468597B2Valid signal for latency sensitive die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·21 claims
- 1356US12321305B2Sideband interface for die-to-die interconnectsINTEL CORP·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 1454US12405912B2Link initialization training and bring up for die-to-die interconnectINTEL CORP·Filed 2022·Granted Sep 2, 2025·0 cites·20 claims
- 1554US2023258716A1Techniques to perform semiconductor testingINTEL CORP·Filed 2023·Application pending·0 cites
- 1653US12316343B2PHY-based retry techniques for die-to-die interfacesINTEL CORP·Filed 2021·Granted May 27, 2025·0 cites·23 claims
- 1752US2022327084A1Die-to-die interconnect protocol layerINTEL CORP·Filed 2022·Application pending·0 cites
- 1851US2023230923A1Microelectronic die including swappable phy circuitry and semiconductor package including sameINTEL CORP·Filed 2022·Application pending·0 cites
- 1949US2024095206A1Assymmetrical data rates for high speed interconnectsINTEL CORP·Filed 2023·Application pending·0 cites
- 2048US2022342841A1Die-to-die adapterCHOUDHARY SWADESH·Filed 2022·Application pending·0 cites
- 2145US2022271912A1Clock phase management for die-to-die (d2d) interconnectPASDAST GERALD·Filed 2022·Application pending·0 cites
- 2244US12159840B2Scalable and interoperable PHYLESS die-to-die IO solutionINTEL CORP·Filed 2020·Granted Dec 3, 2024·0 cites·27 claims
- 2344US2020251159A1Stacked memory device with end to end data bus inversionINTEL CORP·Filed 2020·Application pending·0 cites
- 2443US12298833B2Performance level control in a data processing apparatusINTEL CORP·Filed 2020·Granted May 13, 2025·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →