Inventor · disambiguated record
Laurent Viravaux
Also filed as: VIRAVAUX LAURENT
3 granted patents·1 pending application·0 citations·filing 2003–2020
39Inventor score
Files withSOITEC SILICON ON INSULATOR4
Top patents by PatentIndex Score
4 records- 0149US12176244B2Method for bonding two substratesSOITEC SILICON ON INSULATOR·Filed 2020·Granted Dec 24, 2024·0 cites·16 claims
- 0233US12040194B2Method for etching substrates comprising a thin surface layer, for improving the uniformity of thickness of the layerSOITEC SILICON ON INSULATOR·Filed 2020·Granted Jul 16, 2024·0 cites·14 claims
- 0332US7163897B2Method for assaying elements in a substrate for optics, electronics, or optoelectronicsSOITEC SILICON ON INSULATOR·Filed 2003·Granted Jan 16, 2007·0 cites·17 claims
- 0432US2020083065A1Process for treating an soi substrate in a single wafer cleanerSOITEC SILICON ON INSULATOR·Filed 2019·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →