Inventor · disambiguated record
Lawrence F. Wagner, Jr.
Also filed as: WAGNER JR LAWRENCE F · WAGNER LAWRENCE F · WAGNER LAWRENCE FEDERICK JR
17 granted patents·741 citations·filing 1981–2008
95Inventor score
Top patents by PatentIndex Score
17 records- 0197US5770881ASOI FET design to reduce transient bipolar currentIBM·Filed 1996·Granted Jun 23, 1998·328 cites·21 claims
- 0287US6562666B1Integrated circuits with reduced substrate capacitanceIBM·Filed 2000·Granted May 13, 2003·41 cites·15 claims
- 0386US4415767AMethod and apparatus for speech recognition and reproductionVOTAN·Filed 1981·Granted Nov 15, 1983·102 cites·28 claims
- 0480US7863691B2Merged field effect transistor cells for switchingIBM·Filed 2008·Granted Jan 4, 2011·8 cites·20 claims
- 0578US7139990B2Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extractionIBM·Filed 2004·Granted Nov 21, 2006·29 cites·15 claims
- 0676US4626825ALogarithmic conversion apparatusVLSI TECHNOLOGY INC·Filed 1985·Granted Dec 2, 1986·56 cites·1 claims
- 0765US5446312AVertical-gate CMOS compatible lateral bipolar transistorIBM·Filed 1994·Granted Aug 29, 1995·19 cites·4 claims
- 0864US5258640AGate controlled Schottky barrier diodeIBM·Filed 1992·Granted Nov 2, 1993·24 cites·16 claims
- 0957US4857882AComparator array logicVLSI TECHNOLOGY INC·Filed 1988·Granted Aug 15, 1989·24 cites·4 claims
- 1056US5109524ADigital processor with a four part data register for storing data before and after data conversion and data calculationsVLSI TECHNOLOGY INC·Filed 1988·Granted Apr 28, 1992·24 cites·6 claims
- 1153US5371022AMethod of forming a novel vertical-gate CMOS compatible lateral bipolar transistorIBM·Filed 1994·Granted Dec 6, 1994·11 cites·6 claims
- 1249US6141632AMethod for use in simulation of an SOI deviceIBM·Filed 1999·Granted Oct 31, 2000·21 cites·18 claims
- 1346US6023577AMethod for use in simulation of an SOI deviceIBM·Filed 1997·Granted Feb 8, 2000·18 cites·10 claims
- 1445US6490546B1Method for obtaining DC convergence for SOI FET models in a circuit simulation programIBM·Filed 1999·Granted Dec 3, 2002·19 cites·15 claims
- 1539US4852038ALogarithmic calculating apparatusVLSI TECHOLOGY INC·Filed 1985·Granted Jul 25, 1989·11 cites·7 claims
- 1632US5341023ANovel vertical-gate CMOS compatible lateral bipolar transistorIBM·Filed 1992·Granted Aug 23, 1994·2 cites·3 claims
- 1731US4862346AIndex for a register file with update of addresses using simultaneously received current, change, test, and reload addressesVLSI TECHNOLOGY INC·Filed 1985·Granted Aug 29, 1989·4 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →