Inventor · disambiguated record
Larry Widigen
Also filed as: WIDIGEN LARRY
20 granted patents·1 pending application·644 citations·filing 1993–2001
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0194US5454117AConfigurable branch prediction for a processor performing speculative executionNEXGEN INC·Filed 1993·Granted Sep 26, 1995·171 cites·3 claims
- 0284US6671798B1Configurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 2001·Granted Dec 30, 2003·28 cites·24 claims
- 0383US5623614ABranch prediction cache with multiple entries for returns having multiple callersADVANCED MICRO DEVICES INC·Filed 1993·Granted Apr 22, 1997·93 cites·25 claims
- 0480US6282639B1Configurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 2000·Granted Aug 28, 2001·20 cites·5 claims
- 0574US5802339APipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unitADVANCED MICRO DEVICES INC·Filed 1997·Granted Sep 1, 1998·56 cites·28 claims
- 0667US5418736AOptimized binary adders and comparators for inputs having different widthsNEXGEN INC·Filed 1994·Granted May 23, 1995·37 cites·10 claims
- 0764US5923579AOptimized binary adder and comparator having an implicit constant for an inputADVANCED MICRO DEVICES INC·Filed 1995·Granted Jul 13, 1999·40 cites·3 claims
- 0864US5394351AOptimized binary adder and comparator having an implicit constant for an inputNEXGEN INC·Filed 1994·Granted Feb 28, 1995·35 cites·3 claims
- 0954US6360318B1Configurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 2000·Granted Mar 19, 2002·2 cites·7 claims
- 1053US5919256AOperand cache addressed by the instruction address for reducing latency of read instructionADVANCED MICRO DEVICES INC·Filed 1996·Granted Jul 6, 1999·27 cites·31 claims
- 1152US6041396ASegment descriptor cache addressed by part of the physical address of the desired descriptorADVANCED MICRO DEVICES INC·Filed 1996·Granted Mar 21, 2000·25 cites·24 claims
- 1251US6108777AConfigurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 1998·Granted Aug 22, 2000·16 cites·2 claims
- 1350US5815699AConfigurable branch prediction for a processor performing speculative executionADVANCED MICRO DEVICES INC·Filed 1995·Granted Sep 29, 1998·15 cites·39 claims
- 1448US5590351ASuperscalar execution unit for sequential instruction pointer updates and segment limit checksADVANCED MICRO DEVICES INC·Filed 1994·Granted Dec 31, 1996·20 cites·20 claims
- 1548US5583806AOptimized binary adder for concurrently generating effective and intermediate addressesADVANCED MICRO DEVICES INC·Filed 1995·Granted Dec 10, 1996·21 cites·20 claims
- 1643US5675758AProcessor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operationsADVANCED MICRO DEVICES INC·Filed 1994·Granted Oct 7, 1997·11 cites·20 claims
- 1743US5517440AOptimized binary adders and comparators for inputs having different widthsNEXGEN INC·Filed 1995·Granted May 14, 1996·12 cites·10 claims
- 1841US2002144091A1Method and apparatus for dynamic register management in a processorFiled 2001·Application pending·0 cites
- 1938US5822786AApparatus and method for determining if an operand lies within an expand up or expand down segmentADVANCED MICRO DEVICES INC·Filed 1994·Granted Oct 13, 1998·10 cites·9 claims
- 2034US5699279AOptimized binary adders and comparators for inputs having different widthsADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 16, 1997·5 cites·13 claims
- 2130US6195745B1Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unitADVANCED MICRO DEVICES INC·Filed 1998·Granted Feb 27, 2001·0 cites·35 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →