Inventor · disambiguated record
Lewis W. Dewey, Iii
Also filed as: DEWEY III LEWIS W · DEWEY III LEWIS WILLIAM
17 granted patents·3 pending applications·156 citations·filing 2002–2024
92Inventor score
Top patents by PatentIndex Score
20 records- 0194US8201122B2Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapesDEWEY III LEWIS WILLIAM·Filed 2010·Granted Jun 12, 2012·99 cites·17 claims
- 0289US11176308B1Extracting parasitic capacitance from circuit designsIBM·Filed 2020·Granted Nov 16, 2021·3 cites·20 claims
- 0384US9886541B2Process for improving capacitance extraction performanceIBM·Filed 2015·Granted Feb 6, 2018·4 cites·20 claims
- 0481US10360338B2Method for improving capacitance extraction performance by approximating the effect of distant shapesIBM·Filed 2016·Granted Jul 23, 2019·5 cites·9 claims
- 0578US7290226B2Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristicIBM·Filed 2005·Granted Oct 30, 2007·9 cites·17 claims
- 0676US11314916B2Capacitance extractionIBM·Filed 2020·Granted Apr 26, 2022·1 cites·20 claims
- 0769US10685168B2Capacitance extraction for floating metal in integrated circuitIBM·Filed 2018·Granted Jun 16, 2020·1 cites·20 claims
- 0868US8645899B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2009·Granted Feb 4, 2014·4 cites·8 claims
- 0968US8612918B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2012·Granted Dec 17, 2013·2 cites·17 claims
- 1067US8239804B2Method for calculating capacitance gradients in VLSI layouts using a shape processing engineELFADEL IBRAHIM M·Filed 2009·Granted Aug 7, 2012·4 cites·19 claims
- 1167US7075532B2Robust tetrahedralization and triangulation method with applications in VLSI layout design and manufacturabilityIBM·Filed 2003·Granted Jul 11, 2006·13 cites·14 claims
- 1263US6854099B2Balanced accuracy for extractionIBM·Filed 2002·Granted Feb 8, 2005·10 cites·27 claims
- 1354US2025245411A1Wiring pattern-based parasitic capacitance extractionIBM·Filed 2024·Application pending·0 cites
- 1454US2025156622A1Process of fitting function parameters that facilitates accurate pattern-based 3d capacitance extractionIBM·Filed 2023·Application pending·0 cites
- 1553US10354041B2Process for improving capacitance extraction performanceIBM·Filed 2017·Granted Jul 16, 2019·0 cites·1 claims
- 1651US8479131B2Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contactsDEWEY III LEWIS W·Filed 2011·Granted Jul 2, 2013·1 cites·19 claims
- 1748US8539428B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2012·Granted Sep 17, 2013·0 cites·15 claims
- 1848US8136069B2Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity CorrectionDEWEY III LEWIS WILLIAM·Filed 2009·Granted Mar 13, 2012·0 cites·15 claims
- 1945US10169516B2Methods and computer program products for via capacitance extractionIBM·Filed 2015·Granted Jan 1, 2019·0 cites·20 claims
- 2037US2017177776A1Partitioning of wiring for capacitance extraction without loss in accuracyIBM·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →