Inventor · disambiguated record
Leonard L. Mora
Also filed as: MORA LEONARD · MORA LEONARD L · MORA LEONARD LUCIO
10 granted patents·164 citations·filing 1993–2008
89Inventor score
Technology areasH10W
Top patents by PatentIndex Score
10 records- 0181US5491362APackage structure having accessible chipVLSI TECHNOLOGY INC·Filed 1993·Granted Feb 13, 1996·62 cites·15 claims
- 0275US6891260B1Integrated circuit package substrate with high density routing mechanismLSI LOGIC CORP·Filed 2002·Granted May 10, 2005·28 cites·15 claims
- 0365US6777802B1Integrated circuit package substrate with multiple voltage suppliesLSI LOGIC CORP·Filed 2002·Granted Aug 17, 2004·18 cites·20 claims
- 0462US5687474AMethod of assembling and cooling a package structure with accessible chipVLSI TECHNOLOGY INC·Filed 1996·Granted Nov 18, 1997·25 cites·10 claims
- 0561US6479319B1Contact escape patternLSI LOGIC CORP·Filed 2001·Granted Nov 12, 2002·11 cites·5 claims
- 0660US7750460B2Ball grid array package layout supporting many voltage splits and flexible split locationsLSI CORP·Filed 2008·Granted Jul 6, 2010·2 cites·20 claims
- 0755US7804167B2Wire bond integrated circuit package for high speed I/OLSI LOGIC CORP·Filed 2006·Granted Sep 28, 2010·1 cites·17 claims
- 0850US5539151AReinforced sealing technique for an integrated-circuit packageVLSI TECHNOLOGY INC·Filed 1993·Granted Jul 23, 1996·17 cites·44 claims
- 0936US6748576B2Active trace reroutingLSI LOGIC CORP·Filed 2002·Granted Jun 8, 2004·0 cites·12 claims
- 1029US6264778B1Reinforced sealing technique for an integrated circuit packagePHILIPS ELECTRONICS NA·Filed 1994·Granted Jul 24, 2001·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →