Inventor · disambiguated record
Lisa C. Heller
Also filed as: HELLER LISA C · HELLER LISA CRANTON
182 granted patents·3 pending applications·1,489 citations·filing 1990–2024
99Inventor score
Top patents by PatentIndex Score
185 records- 0198US7197601B2Method, system and program product for invalidating a range of selected storage translation table entriesIBM·Filed 2005·Granted Mar 27, 2007·81 cites·57 claims
- 0296US9697135B2Suppressing virtual address translation utilizing bits and instruction taggingIBM·Filed 2016·Granted Jul 4, 2017·17 cites·18 claims
- 0396US8364912B2Use of test protection instruction in computing environments that support pageable guestsIBM·Filed 2011·Granted Jan 29, 2013·24 cites·12 claims
- 0496US8176279B2Managing use of storage by multiple pageable guests of a computing environmentFARRELL MARK S·Filed 2008·Granted May 8, 2012·30 cites·20 claims
- 0596US8086811B2Optimizations of a perform frame management function issued by pageable guestsGAINEY JR CHARLES W·Filed 2008·Granted Dec 27, 2011·35 cites·18 claims
- 0695US8909899B2Emulating execution of a perform frame management instructionIBM·Filed 2013·Granted Dec 9, 2014·22 cites·20 claims
- 0795US7284100B2Invalidating storage, clearing buffer entries, and an instruction thereforIBM·Filed 2003·Granted Oct 16, 2007·74 cites·72 claims
- 0894US10241910B2Creating a dynamic address translation with translation exception qualifiersIBM·Filed 2017·Granted Mar 26, 2019·8 cites·20 claims
- 0994US9459875B2Dynamic enablement of multithreadingIBM·Filed 2015·Granted Oct 4, 2016·10 cites·8 claims
- 1094US9330018B2Suppressing virtual address translation utilizing bits and instruction taggingIBM·Filed 2013·Granted May 3, 2016·22 cites·5 claims
- 1194US9092382B2Reducing microprocessor performance loss due to translation table coherency in a multi-processor systemIBM·Filed 2012·Granted Jul 28, 2015·22 cites·12 claims
- 1294US8935504B1Execution of a perform frame management function instructionIBM·Filed 2013·Granted Jan 13, 2015·11 cites·20 claims
- 1394US8452942B2Invalidating a range of two or more translation table entries and instruction thereforeSLEGEL TIMOTHY J·Filed 2012·Granted May 28, 2013·22 cites·20 claims
- 1494US8103851B2Dynamic address translation with translation table entry format control for indentifying format of the translation table entryGREINER DAN F·Filed 2008·Granted Jan 24, 2012·30 cites·27 claims
- 1593US9330017B2Suppressing virtual address translation utilizing bits and instruction taggingIBM·Filed 2012·Granted May 3, 2016·19 cites·10 claims
- 1693US8677077B2Use of test protection instruction in computing environments that support pageable guestsIBM·Filed 2013·Granted Mar 18, 2014·10 cites·17 claims
- 1793US8495326B2Execution of a perform frame management function instructionGAINEY JR CHARLES W·Filed 2012·Granted Jul 23, 2013·10 cites·20 claims
- 1893US8478966B2Query sampling information instructionBARTIK JANE H·Filed 2010·Granted Jul 2, 2013·13 cites·20 claims
- 1993US8041923B2Load page table entry address instruction execution based on an address translation format control fieldIBM·Filed 2008·Granted Oct 18, 2011·25 cites·24 claims
- 2093US7827321B2Central processing unit measurement facilityIBM·Filed 2008·Granted Nov 2, 2010·20 cites·20 claims
- 2192US10078585B2Creating a dynamic address translation with translation exception qualifiersIBM·Filed 2015·Granted Sep 18, 2018·6 cites·20 claims
- 2292US9921848B2Address expansion and contraction in a multithreading computer systemIBM·Filed 2014·Granted Mar 20, 2018·14 cites·5 claims
- 2392US9069715B2Reducing microprocessor performance loss due to translation table coherency in a multi-processor systemIBM·Filed 2013·Granted Jun 30, 2015·17 cites·6 claims
- 2492US8239649B2Clearing guest frames absent paging-in to host main storageGAINEY JR CHARLES W·Filed 2011·Granted Aug 7, 2012·13 cites·18 claims
- 2592US8117417B2Dynamic address translation with change record overrideGREINER DAN F·Filed 2008·Granted Feb 14, 2012·21 cites·21 claims
- 2691US9804847B2Thread context preservation in a multithreading computer systemIBM·Filed 2015·Granted Oct 31, 2017·7 cites·8 claims
- 2791US9778869B2Managing storage protection faultsIBM·Filed 2017·Granted Oct 3, 2017·4 cites·20 claims
- 2891US9092351B2Creating a dynamic address translation with translation exception qualifierIBM·Filed 2014·Granted Jul 28, 2015·9 cites·16 claims
- 2991US8489853B2Executing a perform frame management instructionGREINER DAN F·Filed 2012·Granted Jul 16, 2013·10 cites·20 claims
- 3091US8387049B2Facilitating processing within computing environments supporting pageable guestsIBM·Filed 2005·Granted Feb 26, 2013·21 cites·35 claims
- 3191US8380907B2Method, system and computer program product for providing filtering of GUEST2 quiesce requestsIBM·Filed 2008·Granted Feb 19, 2013·25 cites·14 claims
- 3291US8176280B2Use of test protection instruction in computing environments that support pageable guestsFARRELL MARK S·Filed 2008·Granted May 8, 2012·14 cites·20 claims
- 3390US9542260B2Managing storage protection faultsIBM·Filed 2015·Granted Jan 10, 2017·4 cites·20 claims
- 3490US8972670B2Use of test protection instruction in computing environments that support pageable guestsIBM·Filed 2013·Granted Mar 3, 2015·7 cites·20 claims
- 3590US8417916B2Perform frame management function instruction for setting storage keys and clearing blocks of main storageGREINER DAN F·Filed 2008·Granted Apr 9, 2013·22 cites·21 claims
- 3690US8151083B2Dynamic address translation with frame managementGREINER DAN F·Filed 2008·Granted Apr 3, 2012·17 cites·26 claims
- 3789US11150905B2Efficiency for coordinated start interpretive execution exit for a multithreaded processorIBM·Filed 2017·Granted Oct 19, 2021·4 cites·9 claims
- 3889US10223281B2Increasing the scope of local purges of structures associated with address translationIBM·Filed 2016·Granted Mar 5, 2019·5 cites·20 claims
- 3989US10176006B2Delaying purging of structures associated with address translationIBM·Filed 2016·Granted Jan 8, 2019·6 cites·20 claims
- 4089US8806178B2Set sampling controls instructionIBM·Filed 2013·Granted Aug 12, 2014·6 cites·20 claims
- 4189US8516227B2Set program parameter instructionBARTIK JANE H·Filed 2010·Granted Aug 20, 2013·7 cites·20 claims
- 4289US8417837B2Set sampling controls instructionBARTIK JANE H·Filed 2010·Granted Apr 9, 2013·8 cites·25 claims
- 4389US8032716B2System, method and computer program product for providing a new quiesce stateIBM·Filed 2008·Granted Oct 4, 2011·20 cites·15 claims
- 4489US7281115B2Method, system and program product for clearing selected storage translation buffer entriesIBM·Filed 2005·Granted Oct 9, 2007·14 cites·9 claims
- 4589US6996698B2Blocking processing restrictions based on addressesIBM·Filed 2003·Granted Feb 7, 2006·51 cites·44 claims
- 4689US5465374AProcessor for processing data string by byte-by-byteIBM·Filed 1993·Granted Nov 7, 1995·131 cites·6 claims
- 4788US10282305B2Selective purging of entries of structures associated with address translation in a virtualized environmentIBM·Filed 2016·Granted May 7, 2019·6 cites·20 claims
- 4888US9354873B2Performing a clear operation absent host interventionIBM·Filed 2016·Granted May 31, 2016·3 cites·20 claims
- 4988US8707000B2Execution of a perform frame management function instructionIBM·Filed 2013·Granted Apr 22, 2014·5 cites·12 claims
- 5087US10572392B2Increasing the scope of local purges of structures associated with address translationIBM·Filed 2018·Granted Feb 25, 2020·3 cites·20 claims
Showing the top 50 of 185 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Lisa C. Heller files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →