Inventor · disambiguated record
Linda Milor
Also filed as: MILOR LINDA · MILOR LINDA S · MILOR LINDA SUSAN
6 granted patents·2 pending applications·78 citations·filing 1997–2017
82Inventor score
Top patents by PatentIndex Score
8 records- 0175US6448098B1Detection of undesired connection between conductive structures within multiple layers on a semiconductor waferADVANCED MICRO DEVICES INC·Filed 2000·Granted Sep 10, 2002·24 cites·8 claims
- 0266US5886909ADefect diagnosis using simulation for IC yield improvementADVANCED MICRO DEVICES INC·Filed 1997·Granted Mar 23, 1999·33 cites·27 claims
- 0364US10303541B2Technologies for estimating remaining life of integrated circuits using on-chip memoryGEORGIA TECH RES INST·Filed 2017·Granted May 28, 2019·2 cites·23 claims
- 0451US6054721ADetection of undesired connection between conductive structures within multiple layers on a semiconductor waferADVANCED MICRO DEVICES INC·Filed 1999·Granted Apr 25, 2000·17 cites·20 claims
- 0540US10514973B2Memory and logic lifetime simulation systems and methodsGEORGIA TECH RES INST·Filed 2017·Granted Dec 24, 2019·0 cites·21 claims
- 0636US2002073394A1Methodology for increasing yield, manufacturability, and performance of integrated circuits through correction of photolithographic masksFiled 2000·Application pending·0 cites
- 0731US2002073388A1Methodology to improve the performance of integrated circuits by exploiting systematic process non-uniformityFiled 2000·Application pending·0 cites
- 0830US5986477AMethod and system for providing an interconnect layout to reduce delays in logic circuitsADVANCED MICRO DEVICES INC·Filed 1997·Granted Nov 16, 1999·2 cites·26 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →