Inventor · disambiguated record
Lidia Warnes
Also filed as: WARNES LIDIA · WARNES LIDIA M · WARNES LIDIA MIHAELA
37 granted patents·10 pending applications·293 citations·filing 2003–2023
97Inventor score
Files withINTEL CORP11HEWLETT PACKARD DEVELOPMENT CO10HEWLETT PACKARD ENTPR DEV LP10WARNES LIDIA4HEWLETT PACKARD DEVELOPMENT CO LP2
Top patents by PatentIndex Score
47 records- 0195US10699796B2Validation of a repair to a selected row of dataHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Granted Jun 30, 2020·28 cites·12 claims
- 0293US8116144B2Memory module having a memory device configurable to different data pin configurationsSHAW MARK E·Filed 2008·Granted Feb 14, 2012·42 cites·16 claims
- 0392US7739441B1Communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocolHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Jun 15, 2010·30 cites·18 claims
- 0491US8539145B1Increasing the number of ranks per channelWARNES LIDIA·Filed 2009·Granted Sep 17, 2013·51 cites·17 claims
- 0587US8473791B2Redundant memory to mask DRAM failuresSHAW MARK·Filed 2007·Granted Jun 25, 2013·19 cites·9 claims
- 0687US7711887B1Employing a native fully buffered dual in-line memory module protocol to write parallel protocol memory module channelsHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted May 4, 2010·18 cites·18 claims
- 0786US7996602B1Parallel memory device rank selectionHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Aug 9, 2011·16 cites·2 claims
- 0885US11573722B2Tenant based allocation for pooled memoryINTEL CORP·Filed 2020·Granted Feb 7, 2023·2 cites·18 claims
- 0984US9442801B2Platform error correctionHEWLETT PACKARD DEVELOPMENT CO LP·Filed 2014·Granted Sep 13, 2016·7 cites·18 claims
- 1082US10402124B2Dynamically composable computing system, a data center, and method for dynamically composing a computing systemINTEL CORP·Filed 2017·Granted Sep 3, 2019·3 cites·25 claims
- 1180US7741867B2Differential on-line terminationHEWLETT PACKARD DEVELOPMENT CO·Filed 2008·Granted Jun 22, 2010·9 cites·15 claims
- 1278US11074188B2Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memoryINTEL CORP·Filed 2019·Granted Jul 27, 2021·2 cites·20 claims
- 1378US8225031B2Memory module including environmental optimizationLEE TEDDY·Filed 2008·Granted Jul 17, 2012·14 cites·13 claims
- 1475US11693721B2Creating robustness scores for selected portions of a computing infrastructureINTEL CORP·Filed 2021·Granted Jul 4, 2023·1 cites·25 claims
- 1575US9405339B1Power controllerESPINOZA-IBARRA RICARDO ERNESTO·Filed 2007·Granted Aug 2, 2016·9 cites·20 claims
- 1674US9941023B2Post package repair (PPR) data in non-volatile memoryHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Granted Apr 10, 2018·4 cites·8 claims
- 1773US11983408B2Ballooning for multi-tiered pooled memoryINTEL CORP·Filed 2023·Granted May 14, 2024·0 cites·20 claims
- 1873US8018753B2Memory module including voltage sense monitoring interfaceHEWLETT PACKARD DEVELOPMENT CO·Filed 2008·Granted Sep 13, 2011·8 cites·5 claims
- 1971US8151009B2Serial connection external interface from printed circuit board translation to parallel memory protocolGOLDSTEIN MARTIN·Filed 2007·Granted Apr 3, 2012·6 cites·14 claims
- 2071US8020053B2On-line memory testingHEWLETT PACKARD DEVELOPMENT CO·Filed 2008·Granted Sep 13, 2011·7 cites·20 claims
- 2169US8812915B2Determining whether a right to use memory modules in a reliability mode has been acquiredHEWLETT PACKARD DEVELOPMENT CO·Filed 2012·Granted Aug 19, 2014·2 cites·15 claims
- 2266US8892942B2Rank sparing system and methodWARNES LIDIA·Filed 2007·Granted Nov 18, 2014·6 cites·23 claims
- 2364US11681439B2Ballooning for multi-tiered pooled memoryINTEL CORP·Filed 2020·Granted Jun 20, 2023·0 cites·20 claims
- 2463US10657003B2Partial backup during runtime for memory modules with volatile memory and non-volatile memoryHEWLETT PACKARD ENTPR DEV LP·Filed 2015·Granted May 19, 2020·1 cites·11 claims
- 2562US10891185B2Error counters on a memory deviceHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Granted Jan 12, 2021·2 cites·12 claims
- 2662US10068661B2Post package repair (PPR) data in non-volatile memoryHEWLETT PACKARD ENTPR DEV LP·Filed 2018·Granted Sep 4, 2018·1 cites·10 claims
- 2759US12455821B2Memory access tracingINTEL CORP·Filed 2022·Granted Oct 28, 2025·0 cites·18 claims
- 2856US12417121B2Memory pool managementINTEL CORP·Filed 2021·Granted Sep 16, 2025·0 cites·21 claims
- 2954US12443537B2Method to minimize hot/cold page detection overhead on running workloadsINTEL CORP·Filed 2021·Granted Oct 14, 2025·0 cites·20 claims
- 3053US10481807B2Status for generated data imageHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Granted Nov 19, 2019·0 cites·12 claims
- 3153US9292392B2Memory module that includes a memory module copy engine for copying data from an active memory die to a spare memory dieWARNES LIDIA·Filed 2011·Granted Mar 22, 2016·1 cites·14 claims
- 3253US7729126B2Modular DIMM carrier and riser slotHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Jun 1, 2010·4 cites·9 claims
- 3352US10176043B2Memory controllerHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Granted Jan 8, 2019·0 cites·16 claims
- 3451US2017250223A1A resistive random-access memory in printed circuit boardHEWLETT PACKARD DEVELOPMENT CO LP·Filed 2014·Application pending·0 cites
- 3550US9778982B2Memory erasure information in cache linesHEWLETT PACKARD ENTPR DEV LP·Filed 2013·Granted Oct 3, 2017·0 cites·14 claims
- 3649US2017336976A1Determining resting times for memory blocksHEWLETT PACKARD ENTPR DEV LP·Filed 2014·Application pending·0 cites
- 3748US12373335B2Memory thin provisioning using memory poolsINTEL CORP·Filed 2019·Granted Jul 29, 2025·0 cites·17 claims
- 3844US2009027844A1Translator for supporting different memory protocolsCHEN HAU JIUN·Filed 2007·Application pending·0 cites
- 3942US8275956B2Parallel memory device rank selectionWARNES LIDIA·Filed 2011·Granted Sep 25, 2012·0 cites·10 claims
- 4041US10592364B2Handling errors during run time backupsHEWLETT PACKARD ENTPR DEV LP·Filed 2015·Granted Mar 17, 2020·0 cites·12 claims
- 4141US2005052912A1Circuit and system for addressing memory modulesFiled 2003·Application pending·0 cites
- 4240US2023195528A1Method and apparatus to perform workload management in a disaggregated computing systemINTEL CORP·Filed 2021·Application pending·0 cites
- 4340US2005085007A1Joining material stencil and method of useFiled 2003·Application pending·0 cites
- 4440US2008101037A1Securing object relative to PC board using retention device attached to surface-mounted attachment mechanismsAUGUSTIN THOM·Filed 2006·Application pending·0 cites
- 4536US2015294711A1Performing refresh of a memory device in response to access of dataHEWLETT PACKARD DEVELOPMENT CO·Filed 2012·Application pending·0 cites
- 4635US2014325315A1Memory module buffer data storageWARNES LIDIA M·Filed 2012·Application pending·0 cites
- 4735US2015363261A1Ram refresh rateHEWLETT PACKARD DEVELOPMENT CO·Filed 2013·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →