Inventor · disambiguated record
Loke Yip Foo
Also filed as: Foo Loke Yip
10 granted patents·3 pending applications·13 citations·filing 2004–2024
81Inventor score
Top patents by PatentIndex Score
13 records- 0182US2025022774A1Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling sameALTERA CORP·Filed 2024·Application pending·0 cites
- 0281US11393758B2Power delivery for embedded interconnect bridge devices and methodsINTEL CORP·Filed 2019·Granted Jul 19, 2022·3 cites·13 claims
- 0377US12237245B2Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling sameINTEL CORP·Filed 2022·Granted Feb 25, 2025·0 cites·20 claims
- 0476US9978735B2Interconnection of an embedded dieALTERA CORP·Filed 2016·Granted May 22, 2018·3 cites·20 claims
- 0572US12125768B2Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling sameALTERA CORP·Filed 2021·Granted Oct 22, 2024·0 cites·14 claims
- 0660US11107751B2Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling sameINTEL CORP·Filed 2019·Granted Aug 31, 2021·0 cites·21 claims
- 0758US7081772B1Optimizing logic in non-reprogrammable logic devicesALTERA CORP·Filed 2004·Granted Jul 25, 2006·7 cites·16 claims
- 0855US11805602B2Chip assembliesINTEL CORP·Filed 2020·Granted Oct 31, 2023·0 cites·20 claims
- 0952US2024063148A1Deep trench capacitor bridge for multi-chip packageINTEL CORP·Filed 2022·Application pending·0 cites
- 1051US11527481B2Stacked semiconductor package with flyover bridgeINTEL CORP·Filed 2020·Granted Dec 13, 2022·0 cites·17 claims
- 1149US2023119525A1Package substrate with power delivery networkINTEL CORP·Filed 2021·Application pending·0 cites
- 1248US11562959B2Embedded dual-sided interconnect bridges for integrated-circuit packagesINTEL CORP·Filed 2020·Granted Jan 24, 2023·0 cites·17 claims
- 1339US9842181B1Method to optimize general-purpose input/output interface pad assignments for integrated circuitALTERA CORP·Filed 2016·Granted Dec 12, 2017·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →