Inventor · disambiguated record
Lonny Lambrecht
Also filed as: LAMBRECHT LONNY · LAMBRECHT LONNY J
19 granted patents·3 pending applications·43 citations·filing 2002–2017
92Inventor score
Top patents by PatentIndex Score
22 records- 0188US10216653B2Pre-transmission data reordering for a serial interfaceIBM·Filed 2017·Granted Feb 26, 2019·5 cites·19 claims
- 0278US7467277B2Memory controller operating in a system with a variable system clockIBM·Filed 2006·Granted Dec 16, 2008·8 cites·9 claims
- 0376US7716430B2Separate handling of read and write of read-modify-writeIBM·Filed 2008·Granted May 11, 2010·6 cites·15 claims
- 0471US9563594B2Intercomponent data communication between multiple time zonesIBM·Filed 2014·Granted Feb 7, 2017·2 cites·13 claims
- 0571US7761682B2Memory controller operating in a system with a variable system clockIBM·Filed 2008·Granted Jul 20, 2010·4 cites·10 claims
- 0660US9552304B2Maintaining command order of address translation cache misses and subsequent hitsIBM·Filed 2015·Granted Jan 24, 2017·1 cites·7 claims
- 0758US7676639B2Separate handling of read and write of read-modify-writeIBM·Filed 2008·Granted Mar 9, 2010·1 cites·7 claims
- 0857US7272692B2Arbitration scheme for memory command selectorsIBM·Filed 2004·Granted Sep 18, 2007·6 cites·19 claims
- 0956US9582442B2Intercomponent data communication between different processorsIBM·Filed 2014·Granted Feb 28, 2017·0 cites·14 claims
- 1056US7363442B2Separate handling of read and write of read-modify-writeIBM·Filed 2004·Granted Apr 22, 2008·4 cites·2 claims
- 1156US7190699B2Method and apparatus for implementing multiple credit levels over multiple queuesIBM·Filed 2002·Granted Mar 13, 2007·4 cites·17 claims
- 1255US9569394B2Intercomponent data communicationIBM·Filed 2014·Granted Feb 14, 2017·0 cites·7 claims
- 1355US9384157B2Intercomponent data communicationIBM·Filed 2014·Granted Jul 5, 2016·0 cites·6 claims
- 1454US9626322B2Interconnection network topology for large scale high performance computing (HPC) systemsIBM·Filed 2014·Granted Apr 18, 2017·0 cites·10 claims
- 1553US9519605B2Interconnection network topology for large scale high performance computing (HPC) systemsIBM·Filed 2014·Granted Dec 13, 2016·0 cites·10 claims
- 1652US7266650B2Method, apparatus, and computer program product for implementing enhanced circular queue using loop countsIBM·Filed 2004·Granted Sep 4, 2007·2 cites·9 claims
- 1747US10268617B2Frame format for a serial interfaceIBM·Filed 2017·Granted Apr 23, 2019·0 cites·16 claims
- 1846US2006129764A1Methods and apparatus for storing a commandIBM·Filed 2004·Application pending·0 cites
- 1942US2007220361A1Method and apparatus for guaranteeing memory bandwidth for trace dataIBM·Filed 2006·Application pending·0 cites
- 2040US9471508B1Maintaining command order of address translation cache misses and subsequent hitsIBM·Filed 2015·Granted Oct 18, 2016·0 cites·13 claims
- 2136US8769164B2Methods and apparatus for allocating bandwidth for a network processorALFERNESS MERWIN H·Filed 2003·Granted Jul 1, 2014·0 cites·23 claims
- 2232US2007250283A1Maintenance and Calibration Operations for MemoriesBARNUM MELISSA A·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →