Inventor · disambiguated record
Louise H. Trevillyan
Also filed as: TREVILLYAN LOUISE · TREVILLYAN LOUISE H · TREVILLYAN LOUISE HELEN
20 granted patents·3 pending applications·265 citations·filing 1989–2013
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
23 records- 0193US8271920B2Converged large block and structured synthesis for high performance microprocessor designsCHO MINSIK·Filed 2010·Granted Sep 18, 2012·34 cites·22 claims
- 0292US7581201B2System and method for sign-off timing closure of a VLSI chipIBM·Filed 2007·Granted Aug 25, 2009·35 cites·19 claims
- 0392US7225421B2Clock tree distribution generation by determining allowed placement regions for clocked elementsIBM·Filed 2005·Granted May 29, 2007·38 cites·24 claims
- 0490US7448014B2Design stage mitigation of interconnect variabilityIBM·Filed 2006·Granted Nov 4, 2008·20 cites·7 claims
- 0584US7996812B2Method of minimizing early-mode violations causing minimum impact to a chip designIBM·Filed 2008·Granted Aug 9, 2011·16 cites·18 claims
- 0684US6698003B2Framework for multiple-engine based verification tools for integrated circuitsIBM·Filed 2001·Granted Feb 24, 2004·38 cites·28 claims
- 0783US7895556B2Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routesIBM·Filed 2007·Granted Feb 22, 2011·13 cites·18 claims
- 0877US7451416B2Method and system for designing an electronic circuitIBM·Filed 2006·Granted Nov 11, 2008·7 cites·7 claims
- 0971US8539400B2Routability using multiplexer structuresALPERT CHARLES J·Filed 2011·Granted Sep 17, 2013·3 cites·16 claims
- 1068US7900182B2Method and system for designing an electronic circuitIBM·Filed 2008·Granted Mar 1, 2011·3 cites·18 claims
- 1164US5257201AMethod to efficiently reduce the number of connections in a circuitIBM·Filed 1989·Granted Oct 26, 1993·33 cites·8 claims
- 1261US8407652B2Task-based multi-process design synthesisDRUMM ANTHONY D·Filed 2010·Granted Mar 26, 2013·1 cites·23 claims
- 1361US7685553B2System and method for global circuit routing incorporating estimation of critical area estimate metricsIBM·Filed 2007·Granted Mar 23, 2010·2 cites·34 claims
- 1461US6958545B2Method for reducing wiring congestion in a VLSI chip designIBM·Filed 2004·Granted Oct 25, 2005·8 cites·11 claims
- 1560US7930669B2Stage mitigation of interconnect variabilityIBM·Filed 2008·Granted Apr 19, 2011·1 cites·9 claims
- 1659US8341565B2Task-based multi-process design synthesis with reproducible transformsDRUMM ANTHONY D·Filed 2010·Granted Dec 25, 2012·1 cites·23 claims
- 1758US8392866B2Task-based multi-process design synthesis with notification of transform signaturesDRUMM ANTHONY D·Filed 2010·Granted Mar 5, 2013·1 cites·25 claims
- 1853US8677304B2Task-based multi-process design synthesisIBM·Filed 2013·Granted Mar 18, 2014·0 cites·25 claims
- 1950US8020134B2Method and apparatus for parallel processing of semiconductor chip designsIBM·Filed 2008·Granted Sep 13, 2011·1 cites·14 claims
- 2049US2010257499A1Techniques for fast area-efficient incremental physical synthesisIBM·Filed 2009·Application pending·0 cites
- 2145US2008155486A1Systems and methods for reducing wiring vias during synthesis of electronic designsIBM·Filed 2006·Application pending·0 cites
- 2243US2007234259A1Cell placement in circuit designIBM·Filed 2006·Application pending·0 cites
- 2335US5754824ALogic synthesis for logic array modulesIBM·Filed 1995·Granted May 19, 1998·10 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →