Inventor · disambiguated record
Lukas Daellenbach
Also filed as: DAELLENBACH LUKAS
12 granted patents·1 pending application·42 citations·filing 2008–2022
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
13 records- 0197US10997350B1Semiconductor circuit design and unit pin placementIBM·Filed 2020·Granted May 4, 2021·10 cites·25 claims
- 0289US8423940B2Early noise detection and noise aware routing in circuit designDAELLENBACH LUKAS·Filed 2011·Granted Apr 16, 2013·23 cites·20 claims
- 0383US9418198B1Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)IBM·Filed 2015·Granted Aug 16, 2016·4 cites·12 claims
- 0472US10936773B1Sink-based wire tagging in multi-sink integrated circuit netIBM·Filed 2019·Granted Mar 2, 2021·1 cites·20 claims
- 0566US11354478B2Semiconductor circuit design and unit pin placementIBM·Filed 2021·Granted Jun 7, 2022·0 cites·20 claims
- 0666US10353841B2Optimizing routing of a signal path in a semiconductor deviceIBM·Filed 2016·Granted Jul 16, 2019·1 cites·18 claims
- 0766US10031996B2Timing based net constraints tagging with zero wire load validationIBM·Filed 2016·Granted Jul 24, 2018·1 cites·20 claims
- 0860US8566774B2Optimized buffer placement based on timing and capacitance assertionsDAELLENBACH LUKAS·Filed 2011·Granted Oct 22, 2013·1 cites·10 claims
- 0957US12340161B2Multi-layer integrated circuit routing toolIBM·Filed 2022·Granted Jun 24, 2025·0 cites·23 claims
- 1057US7966597B2Method and system for routing of integrated circuit designIBM·Filed 2008·Granted Jun 21, 2011·1 cites·14 claims
- 1151US9727687B2Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS)IBM·Filed 2015·Granted Aug 8, 2017·0 cites·6 claims
- 1251US8930870B2Optimized buffer placement based on timing and capacitance assertionsIBM·Filed 2013·Granted Jan 6, 2015·0 cites·20 claims
- 1342US2020050730A1Re-routing time critical multi-sink nets in chip designIBM·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →