Inventor · disambiguated record
Mazhar M. Alidina
Also filed as: ALIDINA MAZHAR · ALIDINA MAZHAR M
10 granted patents·699 citations·filing 1997–2001
91Inventor score
Top patents by PatentIndex Score
10 records- 0196US5991785ADetermining an extremum value and its index in an array using a dual-accumulation processorLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 23, 1999·490 cites·16 claims
- 0279US6851046B1Jumping to a recombine target address which is encoded in a ternary branch instructionGLOBESPAN VIRATA INC·Filed 2001·Granted Feb 1, 2005·29 cites·15 claims
- 0365US5987490AMac processor with efficient Viterbi ACS operation and automatic traceback storeLUCENT TECHNOLOGIES INC·Filed 1997·Granted Nov 16, 1999·48 cites·17 claims
- 0463US5889689AHierarchical carry-select, three-input saturationLUCENT TECHNOLOGIES INC·Filed 1997·Granted Mar 30, 1999·43 cites·17 claims
- 0559US6446193B1Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architectureAGERE SYST GUARDIAN CORP·Filed 1997·Granted Sep 3, 2002·35 cites·24 claims
- 0655US6530014B2Near-orthogonal dual-MAC instruction set architecture with minimal encoding bitsAGERE SYSTEMS INC·Filed 1998·Granted Mar 4, 2003·30 cites·14 claims
- 0748US6819971B1Fast computation of overflow flag in a bit manipulation unitAGERE SYSTEMS INC·Filed 2000·Granted Nov 16, 2004·1 cites·8 claims
- 0837US6175912B1Accumulator read port arbitration logicLUCENT TECHNOLOGIES INC·Filed 1997·Granted Jan 16, 2001·10 cites·17 claims
- 0937US6064714AShifter capable of split operationLUCENT TECHNOLOGIES INC·Filed 1998·Granted May 16, 2000·5 cites·30 claims
- 1034US6801995B1Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codesAGERE SYSTEMS INC·Filed 1998·Granted Oct 5, 2004·8 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →