Inventor · disambiguated record
Mathew R. Arcoleo
Also filed as: ARCOLEO MATHEW · ARCOLEO MATHEW R
15 granted patents·450 citations·filing 1995–2020
94Inventor score
Top patents by PatentIndex Score
15 records- 0193US5864506AMemory having selectable output strengthCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Jan 26, 1999·115 cites·20 claims
- 0287US6262937B1Synchronous random access memory having a read/write address bus and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jul 17, 2001·57 cites·14 claims
- 0387US5732027AMemory having selectable output strengthCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Mar 24, 1998·69 cites·10 claims
- 0481US6385128B1Random access memory having a read/write address bus and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted May 7, 2002·25 cites·6 claims
- 0576US5852579AMethod and circuit for preventing and/or inhibiting contention in a system employing a random access memoryCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Dec 22, 1998·37 cites·19 claims
- 0671US6640266B2Method and device for performing write operations to synchronous burst memoryCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Oct 28, 2003·21 cites·20 claims
- 0771US6360307B1Circuit architecture and method of writing data to a memoryCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Mar 19, 2002·31 cites·5 claims
- 0866US6262936B1Random access memory having independent read port and write port and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jul 17, 2001·21 cites·18 claims
- 0965US12321608B2Read cache memoryMICRON TECHNOLOGY INC·Filed 2020·Granted Jun 3, 2025·0 cites·13 claims
- 1065US9710173B2Read cache memory with DRAM class promotionMICRON TECHNOLOGY INC·Filed 2014·Granted Jul 18, 2017·2 cites·12 claims
- 1161US6167528AProgrammably timed storage element for integrated circuit input/outputCYPRESS SEMICONDUCTOR·Filed 1995·Granted Dec 26, 2000·39 cites·21 claims
- 1257US5691654AVoltage level translator circuitCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Nov 25, 1997·15 cites·16 claims
- 1347US10768828B2Data movement between volatile and non-volatile memory in a read cache memoryMICRON TECHNOLOGY INC·Filed 2017·Granted Sep 8, 2020·0 cites·17 claims
- 1447US6445645B2Random access memory having independent read port and write port and process for writing to and reading from the sameCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Sep 3, 2002·4 cites·5 claims
- 1542US5963499ACascadable multi-channel network memory with dynamic allocationCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Oct 5, 1999·14 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →