Inventor · disambiguated record
Matthew Berzins
Also filed as: BERZINS MATTHEW · BERZINS MATTHEW S · BERZINS MATTHEW STEPHEN
33 granted patents·2 pending applications·239 citations·filing 2002–2022
96Inventor score
Files withSAMSUNG ELECTRONICS CO LTD17CYPRESS SEMICONDUCTOR CORP6BERZINS MATTHEW3BERZINS MATTHEW S2FREESCALE SEMICONDUCTOR INC2
Top patents by PatentIndex Score
35 records- 0193US7583121B2Flip-flop having logic state retention during a power down mode and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 1, 2009·40 cites·19 claims
- 0292US8975949B2Integrated clock gater (ICG) using clock cascode complimentary switch logicBERZINS MATTHEW S·Filed 2013·Granted Mar 10, 2015·11 cites·18 claims
- 0391US9473117B2Multi-bit flip-flops and scan chain circuitsKIM MIN-SU·Filed 2015·Granted Oct 18, 2016·8 cites·20 claims
- 0491US9419590B2Low power toggle latch-based flip-flop including integrated clock gating logicSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Aug 16, 2016·16 cites·11 claims
- 0590US9564897B1Apparatus for low power high speed integrated clock gating cellBERZINS MATTHEW·Filed 2016·Granted Feb 7, 2017·13 cites·19 claims
- 0687US7176720B1Low duty cycle distortion differential to CMOS translatorCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Feb 13, 2007·38 cites·17 claims
- 0784US10748889B2Power grid and standard cell co-design structure and methods thereofSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Aug 18, 2020·6 cites·18 claims
- 0884US10298235B2Low power integrated clock gating cell using controlled inverted clockSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted May 21, 2019·5 cites·17 claims
- 0977US10784864B1Low power integrated clock gating system and methodSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Sep 22, 2020·3 cites·9 claims
- 1076US7239178B1Circuit and method for CMOS voltage level translationCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted Jul 3, 2007·9 cites·14 claims
- 1175US9891283B2Multi-bit flip-flops and scan chain circuitsSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Feb 13, 2018·2 cites·19 claims
- 1274US10784198B2Power rail for standard cell blockSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Sep 22, 2020·2 cites·20 claims
- 1374US9904758B2Using deep sub-micron stress effects and proximity effects to create a high performance standard cellBERZINS MATTHEW·Filed 2016·Granted Feb 27, 2018·2 cites·20 claims
- 1473US7826581B1Linearized digital phase-locked loop method for maintaining end of packet time linearityCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Nov 2, 2010·20 cites·21 claims
- 1573US7683697B2Circuitry and method for buffering a power mode control signalFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Mar 23, 2010·7 cites·20 claims
- 1673US7173453B2Method and circuit for translating a differential signal to complementary CMOS levelsCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Feb 6, 2007·16 cites·19 claims
- 1772US10819342B2Low-power low-setup integrated clock gating cell with complex enable selectionSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Oct 27, 2020·2 cites·18 claims
- 1872US9779201B2Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based designMILLAR BRIAN·Filed 2015·Granted Oct 3, 2017·3 cites·16 claims
- 1970US10262723B2System and method for improving scan hold-time violation and low voltage operation in sequential circuitSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Apr 16, 2019·2 cites·20 claims
- 2070US6781465B1Method and apparatus for differential signal detectionCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Aug 24, 2004·17 cites·24 claims
- 2169US8289060B2Pulsed state retention power gating flip-flopTOWER SAMUEL J·Filed 2007·Granted Oct 16, 2012·8 cites·18 claims
- 2269US7394293B1Circuit and method for rapid power up of a differential output driverCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted Jul 1, 2008·6 cites·20 claims
- 2368US10581410B2High speed domino-based flip flopBERZINS MATTHEW·Filed 2016·Granted Mar 3, 2020·2 cites·20 claims
- 2464US11092649B2Method for reducing power consumption in scannable flip-flops without additional circuitrySAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Aug 17, 2021·0 cites·20 claims
- 2561US10353000B2Multi-bit flip-flopsSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Jul 16, 2019·1 cites·20 claims
- 2658US10720204B2System and method for improving scan hold-time violation and low voltage operation in sequential circuitSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Jul 21, 2020·0 cites·20 claims
- 2752US9450578B2Integrated clock gater (ICG) using clock cascode complimentary switch logicSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Sep 20, 2016·0 cites·18 claims
- 2850US2023161940A1Zero diffusion breakSAMSUNG ELECTRONICS CO LTD·Filed 2022·Application pending·0 cites
- 2949US9203382B2Integrated clock gater (ICG) using clock cascode complimentary switch logicBERZINS MATTHEW S·Filed 2015·Granted Dec 1, 2015·0 cites·7 claims
- 3046US10607982B2Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cellSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Mar 31, 2020·0 cites·15 claims
- 3142US10382017B1Dynamic flip flop having data independent P-stack feedbackSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Aug 13, 2019·0 cites·18 claims
- 3242US9793881B2Flip-flop with zero-delay bypass muxWELLS CHRISTINA·Filed 2014·Granted Oct 17, 2017·0 cites·17 claims
- 3340US2018340979A1System and method for reducing power consumption in scannable circuitSAMSUNG ELECTRONICS CO LTD·Filed 2017·Application pending·0 cites
- 3439US9899990B2Semiconductor circuit including flip-flopSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Feb 20, 2018·0 cites·18 claims
- 3530US9768756B2Low power integrated clock gating cell with internal control signalLim James Jung·Filed 2016·Granted Sep 19, 2017·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →