Inventor · disambiguated record
Maarten J. Boersma
Also filed as: BOERSMA MAARTEN · BOERSMA MAARTEN J · BOERSMA MAARTEN JAKOB
47 granted patents·4 pending applications·153 citations·filing 2008–2023
97Inventor score
Top patents by PatentIndex Score
51 records- 0193US9760375B2Register files for storing data operated on by instructions of multiple widthsIBM·Filed 2014·Granted Sep 12, 2017·23 cites·12 claims
- 0293US9740486B2Register files for storing data operated on by instructions of multiple widthsIBM·Filed 2014·Granted Aug 22, 2017·23 cites·13 claims
- 0392US9207995B2Mechanism to speed-up multithreaded execution by register file write port reallocationBOERSMA MAARTEN J·Filed 2011·Granted Dec 8, 2015·26 cites·12 claims
- 0485US11157280B2Dynamic fusion based on operand sizeIBM·Filed 2017·Granted Oct 26, 2021·4 cites·20 claims
- 0584US8245065B2Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is fullNIGGEMEIER TIM·Filed 2009·Granted Aug 14, 2012·17 cites·11 claims
- 0683US11132198B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2019·Granted Sep 28, 2021·2 cites·25 claims
- 0783US9798549B1Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2016·Granted Oct 24, 2017·3 cites·13 claims
- 0879US8291003B2Supporting multiple formats in a floating point processorBOERSMA MAARTEN J·Filed 2008·Granted Oct 16, 2012·11 cites·3 claims
- 0977US8578196B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2012·Granted Nov 5, 2013·3 cites·14 claims
- 1076US8949575B2Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latencyBOERSMA MAARTEN J·Filed 2011·Granted Feb 3, 2015·4 cites·10 claims
- 1176US8244783B2Normalizer shift prediction for log estimate instructionsBOERSMA MAARTEN J·Filed 2008·Granted Aug 14, 2012·8 cites·12 claims
- 1274US9122517B2Fused multiply-adder with booth-encodingBOERSMA MAARTEN J·Filed 2012·Granted Sep 1, 2015·3 cites·8 claims
- 1374US8903882B2Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program productBOERSMA MAARTEN J·Filed 2011·Granted Dec 2, 2014·4 cites·13 claims
- 1474US2023367597A1Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2023·Application pending·0 cites
- 1571US11755325B2Instruction handling for accumulation of register results in a microprocessorIBM·Filed 2021·Granted Sep 12, 2023·0 cites·19 claims
- 1671US9164725B2Apparatus and method for calculating an SHA-2 hash function in a general purpose processorBOERSMA MAARTEN J·Filed 2011·Granted Oct 20, 2015·3 cites·20 claims
- 1771US8806253B2Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independentNIGGEMEIER TIM·Filed 2012·Granted Aug 12, 2014·3 cites·11 claims
- 1871US8346828B2System and method for storing numbers in first and second formats in a register fileIBM·Filed 2008·Granted Jan 1, 2013·5 cites·20 claims
- 1969US8407275B2Fast floating point compare with slower backup for corner casesBOERSMA MAARTEN J·Filed 2008·Granted Mar 26, 2013·4 cites·20 claims
- 2065US8255726B2Zero indication forwarding for floating point unit power reductionBAROWSKI HARRY S·Filed 2008·Granted Aug 28, 2012·3 cites·14 claims
- 2164US8984039B2Residue-based error detection for a processor execution unit that supports vector operationsBOERSMA MAARTEN JAKOB·Filed 2012·Granted Mar 17, 2015·2 cites·11 claims
- 2263US10996953B2Low latency execution of floating-point record form instructionsIBM·Filed 2019·Granted May 4, 2021·0 cites·7 claims
- 2360US10768897B2Arithmetic logic unit for single-cycle fusion operationsIBM·Filed 2019·Granted Sep 8, 2020·0 cites·20 claims
- 2460US8352531B2Efficient forcing of corner cases in a floating point rounderIBM·Filed 2008·Granted Jan 8, 2013·2 cites·13 claims
- 2558US10678547B2Low latency execution of floating-point record form instructionsIBM·Filed 2017·Granted Jun 9, 2020·0 cites·7 claims
- 2658US10671399B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·8 claims
- 2758US10592246B2Low latency execution of floating-point record form instructionsIBM·Filed 2017·Granted Mar 17, 2020·0 cites·10 claims
- 2857US10671398B2Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor coreIBM·Filed 2017·Granted Jun 2, 2020·0 cites·12 claims
- 2956US11157276B2Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entryIBM·Filed 2019·Granted Oct 26, 2021·0 cites·19 claims
- 3056US10169046B2Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2017·Granted Jan 1, 2019·0 cites·12 claims
- 3156US9361267B2Splitable and scalable normalizer for vector dataBOERSMA MAARTEN J·Filed 2013·Granted Jun 7, 2016·0 cites·4 claims
- 3256US9361268B2Splitable and scalable normalizer for vector dataIBM·Filed 2014·Granted Jun 7, 2016·0 cites·5 claims
- 3355US9846614B1ECC scrubbing in a multi-slice microprocessorIBM·Filed 2016·Granted Dec 19, 2017·0 cites·20 claims
- 3455US9753690B2Splitable and scalable normalizer for vector dataIBM·Filed 2016·Granted Sep 5, 2017·0 cites·8 claims
- 3555US9170771B2Residue-based error detection for a processor execution unit that supports vector operationsIBM·Filed 2014·Granted Oct 27, 2015·0 cites·6 claims
- 3654US10545727B2Arithmetic logic unit for single-cycle fusion operationsIBM·Filed 2018·Granted Jan 28, 2020·0 cites·14 claims
- 3754US9256397B2Fused multiply-adder with booth-encodingIBM·Filed 2013·Granted Feb 9, 2016·0 cites·6 claims
- 3854US8977835B2Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latencyIBM·Filed 2013·Granted Mar 10, 2015·0 cites·5 claims
- 3953US8032854B23-stack floorplan for floating point unitIBM·Filed 2008·Granted Oct 4, 2011·0 cites·8 claims
- 4051US11093246B2Banked slice-target register file for wide dataflow execution in a microprocessorIBM·Filed 2019·Granted Aug 17, 2021·0 cites·18 claims
- 4151US10360036B2Cracked execution of move-to-FPSCR instructionsIBM·Filed 2017·Granted Jul 23, 2019·0 cites·20 claims
- 4250US12411996B2Hardware-based implementation of secure hash algorithmsIBM·Filed 2022·Granted Sep 9, 2025·0 cites·16 claims
- 4349US10831496B2Method to execute successive dependent instructions from an instruction stream in a processorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 4448US11561798B2On-the-fly adjustment of issue-write back latency to avoid write back collisions using a result bufferIBM·Filed 2020·Granted Jan 24, 2023·0 cites·20 claims
- 4547US10223196B2ECC scrubbing method in a multi-slice microprocessorIBM·Filed 2017·Granted Mar 5, 2019·0 cites·18 claims
- 4646US11182167B2Method to determine the oldest instruction in an instruction queue of a processor with multiple instruction threadsIBM·Filed 2019·Granted Nov 23, 2021·0 cites·14 claims
- 4746US2024053963A1Hardware-based galois multiplicationIBM·Filed 2022·Application pending·0 cites
- 4844US2024015004A1Hardware-based key generation and storage for cryptographic functionIBM·Filed 2022·Application pending·0 cites
- 4943US8332453B2Shifter with all-one and all-zero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted resultBOERSMA MAARTEN·Filed 2008·Granted Dec 11, 2012·0 cites·15 claims
- 5039US2017364356A1Techniques for implementing store instructions in a multi-slice processor architectureIBM·Filed 2016·Application pending·0 cites
Showing the top 50 of 51 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Maarten J. Boersma files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →