Inventor · disambiguated record
Mark A. Brittain
Also filed as: BRITTAIN MARK A · BRITTAIN MARK ANDREW
26 granted patents·2 pending applications·500 citations·filing 2003–2015
96Inventor score
Top patents by PatentIndex Score
28 records- 0198US7934070B2Streaming reads for early processing in a cascaded memory subsystem with buffered memory devicesIBM·Filed 2007·Granted Apr 26, 2011·79 cites·17 claims
- 0297US7587559B2Systems and methods for memory module power managementIBM·Filed 2006·Granted Sep 8, 2009·63 cites·28 claims
- 0397US7337293B2Streaming reads for early processing in a cascaded memory subsystem with buffered memory devicesIBM·Filed 2005·Granted Feb 26, 2008·69 cites·2 claims
- 0496US7421598B2Dynamic power management via DIMM read operation limiterIBM·Filed 2005·Granted Sep 2, 2008·69 cites·6 claims
- 0595US8055922B2Power management via DIMM read operation limiterIBM·Filed 2008·Granted Nov 8, 2011·39 cites·12 claims
- 0694US7426649B2Power management via DIMM read operation limiterIBM·Filed 2005·Granted Sep 16, 2008·34 cites·6 claims
- 0793US7493456B2Memory queue with supplemental locations for consecutive addressesIBM·Filed 2006·Granted Feb 17, 2009·33 cites·20 claims
- 0887US7631228B2Using bit errors from memory to alter memory command streamIBM·Filed 2006·Granted Dec 8, 2009·17 cites·14 claims
- 0986US7930470B2System to enable a memory hub device to manage thermal conditions at a memory device level transparent to a memory controllerIBM·Filed 2008·Granted Apr 19, 2011·17 cites·18 claims
- 1083US7840860B2Double DRAM bit steering for multiple error correctionsIBM·Filed 2008·Granted Nov 23, 2010·10 cites·19 claims
- 1181US7523364B2Double DRAM bit steering for multiple error correctionsIBM·Filed 2005·Granted Apr 21, 2009·12 cites·1 claims
- 1279US8909874B2Memory reorder queue biasing preceding high latency operationsBRITTAIN MARK A·Filed 2012·Granted Dec 9, 2014·5 cites·14 claims
- 1379US7930469B2System to provide memory system power reduction without reducing overall memory system performanceIBM·Filed 2008·Granted Apr 19, 2011·9 cites·20 claims
- 1476US7925824B2System to reduce latency by running a memory channel frequency fully asynchronous from a memory device frequencyIBM·Filed 2008·Granted Apr 12, 2011·7 cites·20 claims
- 1570US7373471B2Executing background writes to idle DIMMsIBM·Filed 2005·Granted May 13, 2008·4 cites·3 claims
- 1669US8996824B2Memory reorder queue biasing preceding high latency operationsIBM·Filed 2013·Granted Mar 31, 2015·2 cites·7 claims
- 1769US7925826B2System to increase the overall bandwidth of a memory channel by allowing the memory channel to operate at a frequency independent from a memory device frequencyIBM·Filed 2008·Granted Apr 12, 2011·4 cites·20 claims
- 1868US9632954B2Memory queue handling techniques for reducing impact of high-latency memory operationsBRITTAIN MARK A·Filed 2011·Granted Apr 25, 2017·2 cites·28 claims
- 1968US7600091B2Executing background writes to idle DIMMSIBM·Filed 2007·Granted Oct 6, 2009·3 cites·14 claims
- 2067US6904585B2Method for identification and removal of non-timing critical wire routes from congestion regionIBM·Filed 2003·Granted Jun 7, 2005·13 cites·9 claims
- 2164US9785578B2Apparatus and method for controlling access to a memory deviceADVANCED RISC MACH LTD·Filed 2015·Granted Oct 10, 2017·1 cites·27 claims
- 2263US7925825B2System to support a full asynchronous interface within a memory hub deviceIBM·Filed 2008·Granted Apr 12, 2011·2 cites·20 claims
- 2361US7516264B2Programmable bank/timer address folding in memory devicesIBM·Filed 2005·Granted Apr 7, 2009·5 cites·8 claims
- 2453US2014052936A1Memory queue handling techniques for reducing impact of high-latency memory operationsIBM·Filed 2013·Application pending·0 cites
- 2550US8543759B2Method for scheduling memory refresh operations including power statesIBM·Filed 2013·Granted Sep 24, 2013·0 cites·6 claims
- 2647US7571357B2Memory wrap test mode using functional read/write buffersIBM·Filed 2006·Granted Aug 4, 2009·1 cites·20 claims
- 2742US2006179183A1Single burst completion of multiple writes at buffered DIMMsIBM·Filed 2005·Application pending·0 cites
- 2840US8539146B2Apparatus for scheduling memory refresh operations including power statesBRITTAIN MARK A·Filed 2011·Granted Sep 17, 2013·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →